公开(公告)号：US20210064268A1

公开(公告)日：2021-03-04

申请号：US16554707

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F3/06 ,  H04L9/32

Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to encrypt write data received via the communication interface to produce encrypted data, program a portion of the memory cells of the memory array with the encrypted data, read the encrypted data from the portion of the memory cells in response to a memory read request, decrypt the read encrypted data to produce read decrypted data only for portions of the read encrypted data not stored in purged regions of the memory array.

公开(公告)号：US20200319823A1

公开(公告)日：2020-10-08

申请号：US16565021

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F3/06 ,  G06F12/1009

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

公开(公告)号：US11755214B2

公开(公告)日：2023-09-12

申请号：US17702217

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0631 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US11681461B2

公开(公告)日：2023-06-20

申请号：US17532020

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can he determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

公开(公告)号：US11656794B2

公开(公告)日：2023-05-23

申请号：US17140839

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A tinier of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.

公开(公告)号：US11550711B2

公开(公告)日：2023-01-10

申请号：US16565066

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

公开(公告)号：US11520524B2

公开(公告)日：2022-12-06

申请号：US17157539

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for host adaptive memory device optimization are provided. A memory device can maintain a host model of interactions with a host. A set of commands from the host can be evaluated to create a profile of the set of commands. The profile can be compared to the host model to determine an inconsistency between the profile and the host model. An operation of the memory device can then be modified based on the inconsistency.

公开(公告)号：US11513719B2

公开(公告)日：2022-11-29

申请号：US16554707

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F3/06 ,  H04L9/32

Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to encrypt write data received via the communication interface to produce encrypted data, program a portion of the memory cells of the memory array with the encrypted data, read the encrypted data from the portion of the memory cells in response to a memory read request, decrypt the read encrypted data to produce read decrypted data only for portions of the read encrypted data not stored in purged regions of the memory array.

公开(公告)号：US20220350532A1

公开(公告)日：2022-11-03

申请号：US17243321

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Nadav Grosz ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.

公开(公告)号：US11481336B2

公开(公告)日：2022-10-25

申请号：US16544337

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  Jonathan Scott Parry

IPC: G06F21/14 ,  G06F12/14 ,  G06F21/78 ,  G06F12/02

Abstract: Devices and techniques for efficient host assisted logical-to-physical (L2P) mapping are described herein. For example, a command can be executed that results in a change as to which physical address of a memory device corresponds to a logical address. The change can be obfuscated as part of an obfuscated L2P map for the memory device and written to storage on the memory device. The change can then be provided a host from the storage.