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11.发明公开公开(公告)号：US20240334717A1
公开(公告)日：2024-10-03
申请号：US18424713
申请日：2024-01-26
Applicant: Micron Technology, Inc.
Inventor： Kunal R. Parekh , Russell L. Meyer
IPC: H10B80/00 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H10B80/00 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
Abstract: A method of forming a microelectronic device includes forming a first assembly including a semiconductor base structure, a first circuitry region including first devices at a first boundary of the semiconductor base structure, and a second circuitry region including second devices at a second boundary of the semiconductor base structure vertically offset from the first boundary. A microelectronic device structure is formed and includes a stack structure including tiers individually including conductive material and insulative material vertically adjacent the conductive material, and cell pillar structures including semiconductor material vertically extending through the stack structure. The first assembly is attached to the microelectronic device structure to form a second assembly. Microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号：US20230005535A1
公开(公告)日：2023-01-05
申请号：US17864015
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer , Agostino Pirovano , Russell L. Meyer
IPC: G11C13/00 , H01L23/528
Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
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公开(公告)号：US10593399B2
公开(公告)日：2020-03-17
申请号：US15925536
申请日：2018-03-19
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer , Agostino Pirovano , Russell L. Meyer
IPC: G11C13/00 , H01L23/528
Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
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公开(公告)号：US20180040370A1
公开(公告)日：2018-02-08
申请号：US15231518
申请日：2016-08-08
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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公开(公告)号：US11696454B2
公开(公告)日：2023-07-04
申请号：US17306444
申请日：2021-05-03
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Russell L. Meyer , Agostino Pirovano , Lorenzo Fratin
CPC classification number: H10B63/845 , G11C13/003 , G11C13/004 , G11C13/0069 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/823 , H10N70/841 , H10N70/8828 , G11C13/0004 , G11C2213/71
Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
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Patent Agency Ranking
公开(公告)号：US11482280B2
公开(公告)日：2022-10-25
申请号：US16436734
申请日：2019-06-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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公开(公告)号：US20210257408A1
公开(公告)日：2021-08-19
申请号：US17306444
申请日：2021-05-03
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Russell L. Meyer , Agostino Pirovano , Lorenzo Fratin
Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
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公开(公告)号：US10998379B2
公开(公告)日：2021-05-04
申请号：US16656824
申请日：2019-10-18
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Russell L. Meyer , Agostino Pirovano , Lorenzo Fratin
Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
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公开(公告)号：US20200052035A1
公开(公告)日：2020-02-13
申请号：US16656824
申请日：2019-10-18
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Russell L. Meyer , Agostino Pirovano , Lorenzo Fratin
Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
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公开(公告)号：US10446226B2
公开(公告)日：2019-10-15
申请号：US15231518
申请日：2016-08-08
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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