公开(公告)号：US20210264966A1

公开(公告)日：2021-08-26

申请号：US16802306

申请日：2020-02-26

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Sang-Kyun Park

IPC: G11C11/4091 ,  G11C11/4094 ,  H01L27/108

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.

公开(公告)号：US10795759B2

公开(公告)日：2020-10-06

申请号：US16126991

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Atsushi Shimizu ,  Sang-Kyun Park ,  Jongtae Kwak

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  H03M13/00 ,  G11C29/04 ,  G06F13/42

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

公开(公告)号：US20200081769A1

公开(公告)日：2020-03-12

申请号：US16126991

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Atsushi Shimizu ,  Sang-Kyun Park ,  Jongtae Kwak

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  H03M13/00

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.