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公开(公告)号：US12165695B2
公开(公告)日：2024-12-10
申请号：US17737999
申请日：2022-05-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sang-Kyun Park , Yuan He , Hiroshi Akamatsu
IPC: G11C7/00 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4091
Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.
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公开(公告)号：US20230360691A1
公开(公告)日：2023-11-09
申请号：US17737999
申请日：2022-05-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sang-Kyun Park , Yuan He , Hiroshi Akamatsu
IPC: G11C11/4091 , G11C11/4074 , G11C11/408 , G11C7/10
CPC classification number: G11C11/4091 , G11C11/4074 , G11C11/4087 , G11C7/1012
Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.
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公开(公告)号：US20200176047A1
公开(公告)日：2020-06-04
申请号：US16205980
申请日：2018-11-30
Applicant: Micron Technology, Inc.
Inventor： Nathaniel J. Meier , James S. Rehmeyer , Sang-Kyun Park , Makoto Kitayama
IPC: G11C11/406 , G06F3/06 , G11C11/22
Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.
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公开(公告)号：US11367476B2
公开(公告)日：2022-06-21
申请号：US16988970
申请日：2020-08-10
Applicant: Micron Technology, Inc.
Inventor： Sang-Kyun Park , Yuan He
IPC: G11C11/4074 , G11C11/4094 , G11C11/408 , G11C29/02
Abstract: Bit line equalization driver circuits and related apparatuses, methods, and computing systems are disclosed. An apparatus includes an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between a pull-up node and a pull-down node. An output node is electrically connected between the pull-up transistor and the pull-down transistor. The pull-down transistor includes a short length transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor. The apparatus also includes biasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node.
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公开(公告)号：US11170841B2
公开(公告)日：2021-11-09
申请号：US16802306
申请日：2020-02-26
Applicant: Micron Technology, Inc.
Inventor： Yuan He , Sang-Kyun Park
IPC: G11C5/06 , G11C11/4091 , H01L27/108 , G11C11/4094
Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.
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Patent Agency Ranking
公开(公告)号：US20210343323A1
公开(公告)日：2021-11-04
申请号：US17319820
申请日：2021-05-13
Applicant: Micron Technology, Inc.
Inventor： Nathaniel J. Meier , James S. Rehmeyer , Sang-Kyun Park , Makoto Kitayama
IPC: G11C11/406 , G11C11/22 , G06F3/06
Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.
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公开(公告)号：US20210327490A1
公开(公告)日：2021-10-21
申请号：US16853417
申请日：2020-04-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sang-Kyun Park , Tae H. Kim
IPC: G11C11/408 , G11C11/4074 , G11C11/56 , G11C5/06
Abstract: A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well.
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公开(公告)号：US11314591B2
公开(公告)日：2022-04-26
申请号：US17017254
申请日：2020-09-10
Applicant: Micron Technology, Inc.
Inventor： Yoshiro Riho , Atsushi Shimizu , Sang-Kyun Park , Jongtae Kwak
Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.
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公开(公告)号：US11017834B2
公开(公告)日：2021-05-25
申请号：US16205980
申请日：2018-11-30
Applicant: Micron Technology, Inc.
Inventor： Nathaniel J. Meier , James S. Rehmeyer , Sang-Kyun Park , Makoto Kitayama
IPC: G11C11/406 , G06F3/06 , G11C11/22
Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.
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公开(公告)号：US11205470B2
公开(公告)日：2021-12-21
申请号：US16853417
申请日：2020-04-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sang-Kyun Park , Tae H. Kim
IPC: G11C11/408 , G11C5/06 , G11C11/56 , G11C11/4074
Abstract: A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well.
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