公开(公告)号：US20170221542A1

公开(公告)日：2017-08-03

申请号：US15012566

申请日：2016-02-01

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2297

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US20220382658A1

公开(公告)日：2022-12-01

申请号：US17853321

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner ,  Charles L. Ingalls

IPC: G06F11/20 ,  G11C29/44 ,  G11C29/12 ,  G11C29/36 ,  G06F11/14 ,  G11C11/22 ,  G11C29/52

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

公开(公告)号：US11475934B2

公开(公告)日：2022-10-18

申请号：US16693135

申请日：2019-11-22

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

公开(公告)号：US20200035286A1

公开(公告)日：2020-01-30

申请号：US16537090

申请日：2019-08-09

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.

公开(公告)号：US10529402B2

公开(公告)日：2020-01-07

申请号：US16059727

申请日：2018-08-09

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

公开(公告)号：US10431284B2

公开(公告)日：2019-10-01

申请号：US16184460

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.

公开(公告)号：US20190147934A1

公开(公告)日：2019-05-16

申请号：US16184460

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.

公开(公告)号：US20190074046A1

公开(公告)日：2019-03-07

申请号：US16183021

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US20180358077A1

公开(公告)日：2018-12-13

申请号：US16059727

申请日：2018-08-09

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

公开(公告)号：US20180190337A1

公开(公告)日：2018-07-05

申请号：US15855326

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.