公开(公告)号：US20210056405A1

公开(公告)日：2021-02-25

申请号：US16545837

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Sean Stephen Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz

IPC: G06N3/08 ,  G06F21/60

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, inputs for the ANN can be obfuscated for centralized training of a master version of the ANN at a first computing device. A second computing device in the system includes memory that stores a local version of the ANN and user data for inputting into the local version. The second computing device includes a processor that extracts features from the user data and obfuscates the extracted features to generate obfuscated user data. The second device includes a transceiver that transmits the obfuscated user data. The first computing device includes a memory that stores the master version of the ANN, a transceiver that receives obfuscated user data transmitted from the second computing device, and a processor that trains the master version based on the received obfuscated user data using machine learning.

公开(公告)号：US20210056387A1

公开(公告)日：2021-02-25

申请号：US16545813

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06N3/04 ,  G06N20/20

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, changes to local versions of the ANN can be combined with a master version of the ANN. In the system, a first device can include memory that can store the master version, a second device can include memory that can store a local version of the ANN, and there can be many devices that store local versions of the ANN. The second device (or any other device of the system hosting a local version) can include a processor that can train the local version, and a transceiver that can transmit changes to the local version generated from the training. The first device can include a transceiver that can receive the changes to a local version, and a processing device that can combine the received changes with the master version.

公开(公告)号：US12066951B2

公开(公告)日：2024-08-20

申请号：US17964720

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno ,  Sean Stephen Eilert ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Shivam Swami

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/657 ,  G06F2212/68

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

公开(公告)号：US11868268B2

公开(公告)日：2024-01-09

申请号：US17665823

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Sean S. Eilert ,  Hongyu Wang ,  Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Justin M. Eno ,  Shivam Swami

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/657 ,  G06F2212/68

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

公开(公告)号：US11829729B2

公开(公告)日：2023-11-28

申请号：US16888345

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Dmitri Yudanov ,  Sivagnanam Parthasarathy

IPC: G06F7/544 ,  G06F17/16

CPC classification number: G06F7/5443 ,  G06F17/16

Abstract: Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.

公开(公告)号：US20230080030A1

公开(公告)日：2023-03-16

申请号：US18053685

申请日：2022-11-08

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Justin M. Eno

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F3/06 ,  G06F9/50

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

公开(公告)号：US20230033549A1

公开(公告)日：2023-02-02

申请号：US17964720

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno ,  Sean Stephen Eilert ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Shivam Swami

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

公开(公告)号：US11494311B2

公开(公告)日：2022-11-08

申请号：US16573527

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno ,  Sean S. Eilert ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Shivam Swami

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

公开(公告)号：US20210081325A1

公开(公告)日：2021-03-18

申请号：US16573535

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Justin M. Eno

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F3/06 ,  G06F9/50

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

公开(公告)号：US20250077353A1

公开(公告)日：2025-03-06

申请号：US18762284

申请日：2024-07-02

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Ameen D. Akel ,  Shivasankar Gunasekaran ,  Sai Krishna Mylavarapu

IPC: G06F11/10

Abstract: Methods, systems, and devices for data protection techniques in stacked memory architectures are described. A memory system having a stacked memory architecture may include error correction information associated with a data set that includes multiple data segments stored across multiple memory arrays and, in some examples, multiple dies of the memory system. As part of a write operation for a first data segment of a data set, the memory system may retrieve the remaining data segments of the data set and calculate error correction information using the first data segment and the remaining data segments. As part of a read operation for a second data segment of the data set, the memory system may retrieve each data segment of the data set and perform an error correction operation on the data set using the error correction information.