公开(公告)号：US20210175248A1

公开(公告)日：2021-06-10

申请号：US16705449

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Gordon A. Haller ,  William R. Kueber ,  Zachary D. Beaman ,  Christopher G. Shea ,  Taehyun Kim

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/535 ,  H01L23/532 ,  H01L21/768

Abstract: Some embodiments include a method in which a first stack is formed to include a metal-containing first layer, a second layer over the first layer, and a metal-containing third layer over the second layer. A first opening is formed to extend through the second and third layers. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. A second opening is formed through the second stack, and is extended through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack and to the second layer. The second layer is removed to form a conduit. Conductively-doped second semiconductor material is formed within the conduit. Dopant is out-diffused from the conductively-doped second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

公开(公告)号：US11942159B2

公开(公告)日：2024-03-26

申请号：US17591510

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G06F3/06 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/225 ,  G11C16/32

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

公开(公告)号：US20230389312A1

公开(公告)日：2023-11-30

申请号：US17751978

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Taehyun Kim

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed. Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings. Other embodiments, including structure, are disclosed.

公开(公告)号：US20210358950A1

公开(公告)日：2021-11-18

申请号：US17391319

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Gordon A. Haller ,  William R. Kueber ,  Zachary D. Beaman ,  Christopher G. Shea ,  Taehyun Kim

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: Some embodiments include a method in which a first stack is formed to include a metal-containing first layer, a second layer over the first layer, and a metal-containing third layer over the second layer. A first opening is formed to extend through the second and third layers. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. A second opening is formed through the second stack, and is extended through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack and to the second layer. The second layer is removed to form a conduit. Conductively-doped second semiconductor material is formed within the conduit. Dopant is out-diffused from the conductively-doped second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

公开(公告)号：US11088165B2

公开(公告)日：2021-08-10

申请号：US16705449

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Gordon A. Haller ,  William R. Kueber ,  Zachary D. Beaman ,  Christopher G. Shea ,  Taehyun Kim

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: Some embodiments include a method in which a first stack is formed to include a metal-containing first layer, a second layer over the first layer, and a metal-containing third layer over the second layer. A first opening is formed to extend through the second and third layers. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. A second opening is formed through the second stack, and is extended through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack and to the second layer. The second layer is removed to form a conduit. Conductively-doped second semiconductor material is formed within the conduit. Dopant is out-diffused from the conductively-doped second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.