中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.018 seconds)

    Accessing memory devices via switchable channels
    1.
    发明授权
    Accessing memory devices via switchable channels 有权

    公开(公告)号：US12189958B2

    公开(公告)日：2025-01-07

    申请号：US17898160

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

    IPC: G06F3/06

    Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

    SERIAL INTERFACE FOR AN ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM
    2.
    发明申请
    SERIAL INTERFACE FOR AN ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20230075279A1

    公开(公告)日：2023-03-09

    申请号：US17468264

    申请日：2021-09-07

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Chulbum Kim ,  Dustin J. Carter

    IPC: G06F13/16 ,  G06F13/42 ,  G06F12/10

    Abstract: An input/output (I/O) command referencing a logical address of a memory sub-system is received by an active input/output expander (AIOE). The I/O command is received from a memory sub-system controller via the AIOE. The AIOE identifies a physical block address corresponding to the logical block address. The AIOE identifies, among a plurality of memory devices, a memory device associated with the physical block address. The AIOE converts the I/O command received via the serial interface to a parallel interface compliant I/O command. The AIOE sends the parallel interface compliant I/O command to the memory device.

    STATUS CHECK USING CHIP ENABLE PIN
    3.
    发明申请
    STATUS CHECK USING CHIP ENABLE PIN 有权

    公开(公告)号：US20230043140A1

    公开(公告)日：2023-02-09

    申请号：US17963773

    申请日：2022-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

    IPC: G06F13/16 ,  G06F1/26

    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

    PEAK POWER MANAGEMENT PRIORITY OVERRIDE
    5.
    发明公开
    PEAK POWER MANAGEMENT PRIORITY OVERRIDE 审中-公开

    公开(公告)号：US20230350587A1

    公开(公告)日：2023-11-02

    申请号：US18137002

    申请日：2023-04-20

    Applicant: Micron Technology, Inc.

    Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry ,  Chulbum Kim ,  Daniel J. Hubbard ,  Suresh Rajgopal

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0658 ,  G06F3/0679

    Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

    Status check using chip enable pin
    6.
    发明授权
    Status check using chip enable pin 有权

    公开(公告)号：US11500791B2

    公开(公告)日：2022-11-15

    申请号：US17117933

    申请日：2020-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

    IPC: G06F13/16 ,  G06F1/26

    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS
    7.
    发明申请
    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS 有权

    公开(公告)号：US20250077086A1

    公开(公告)日：2025-03-06

    申请号：US18950798

    申请日：2024-11-18

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

    IPC: G06F3/06

    Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, wherein the memory sub-system controller provides a plurality of channel mappings, wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of a plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels; one or more memory devices comprising the plurality of memory channels, wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; and a channel switch circuit coupled between the plurality of the controller channels and the plurality of memory channels, wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing.

Patent Agency Ranking