公开(公告)号：US20240063207A1

公开(公告)日：2024-02-22

申请号：US17892038

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Terrence B. McDaniel ,  Amy R. Griffin ,  Kyle K. Kirby ,  Thiagarajan Raman

IPC: H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/34 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/568 ,  H01L24/11 ,  H01L24/80 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/345 ,  H01L23/3135 ,  H01L2221/68381 ,  H01L2221/68368 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/80006

Abstract: Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

公开(公告)号：US20240055400A1

公开(公告)日：2024-02-15

申请号：US17884475

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Kyle K. Kirby ,  Wei Zhou ,  Thiagarajan Raman

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

公开(公告)号：US20210202430A1

公开(公告)日：2021-07-01

申请号：US16806764

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Thiagarajan Raman

IPC: H01L23/00

Abstract: Semiconductor devices having interconnect structures with narrowed portions configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include an end portion away from the semiconductor die, the end portion having a first cross-sectional area. The pillar structure can further include a narrowed portion between the end portion and the semiconductor die, the narrowed portion having a second cross-sectional area less than the first-cross-sectional area of the end portion. A bond material can be coupled to the end portion of the pillar structure.