公开(公告)号：US11915997B2

公开(公告)日：2024-02-27

申请号：US16990943

申请日：2020-08-11

申请人： Micron Technology, Inc.

发明人： Xiaopeng Qu ,  Hyunsuk Chun ,  Eiichi Nakano

IPC分类号： H01L23/473 ,  H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L21/48 ,  H01L25/18

CPC分类号： H01L23/4735 ,  H01L21/4871 ,  H01L23/3672 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50

摘要： Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.

公开(公告)号：US11848282B2

公开(公告)日：2023-12-19

申请号：US17888906

申请日：2022-08-16

申请人： Micron Technology, Inc.

发明人： Hyunsuk Chun ,  Sheng Wei Yang ,  Shams U. Arifeen

IPC分类号： H01L21/76 ,  H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/768 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/7682 ,  H01L23/49827 ,  H01L23/5329 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02235

摘要： Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

公开(公告)号：US11616028B2

公开(公告)日：2023-03-28

申请号：US17062922

申请日：2020-10-05

申请人： Micron Technology, Inc.

发明人： Shams U. Arifeen ,  Hyunsuk Chun ,  Sheng Wei Yang ,  Keizo Kawakita

IPC分类号： H01L23/00

摘要： Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

公开(公告)号：US11538762B2

公开(公告)日：2022-12-27

申请号：US16751676

申请日：2020-01-24

申请人： Micron Technology, Inc.

发明人： Hyunsuk Chun

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

摘要： Semiconductor devices may include a die including a semiconductor material. The die may include a first active surface including first integrated circuitry on a first side of the die and a second active surface including second integrated circuitry on a second, opposite side of the die. In some embodiments, the die may include two die portions: a first die portion including the first active surface and a second die portion including the second active surface. The first die portion and the second die portion may be joined together with the first active surface facing away from the second active surface.

公开(公告)号：US20220394878A1

公开(公告)日：2022-12-08

申请号：US17819716

申请日：2022-08-15

申请人： Micron Technology, Inc.

发明人： Xiaopeng Qu ,  Hyunsuk Chun

IPC分类号： H05K7/20 ,  H01L23/473 ,  H01R12/72

摘要： A semiconductor component system includes a motherboard and a cooling system mounted to the motherboard. The cooling system includes sidewalls projecting from the motherboard. A sub-motherboard extends between the sidewalls and is spaced apart from the motherboard. The sidewalls and the sub-motherboard define a cooling channel over the motherboard. A connector is attached to the sub-motherboard and is configured to receive a semiconductor device daughterboard. The connector has contacts to electrically couple the semiconductor device daughterboard to the sub-motherboard.

公开(公告)号：US11515171B2

公开(公告)日：2022-11-29

申请号：US16895751

申请日：2020-06-08

申请人： Micron Technology, Inc.

发明人： Xiaopeng Qu ,  Hyunsuk Chun ,  Brandon P. Wirz ,  Andrew M. Bayless

IPC分类号： H01L21/447 ,  H01L21/67 ,  H01L21/033 ,  B23K20/02

摘要： This patent application relates to methods and apparatus for temperature modification and reduction of contamination in bonding stacked microelectronic devices with heat applied from a bond head of a thermocompression bonding tool. The stack is substantially enclosed within a skirt carried by the bond head to reduce heat loss and contaminants from the stack, and heat may be added from the skirt.

公开(公告)号：US20210407882A1

公开(公告)日：2021-12-30

申请号：US17061435

申请日：2020-10-01

申请人： Micron Technology, Inc.

发明人： Hyunsuk Chun ,  Xiaopeng Qu ,  Chan H. Yoo

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

摘要： Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

公开(公告)号：US10784212B2

公开(公告)日：2020-09-22

申请号：US16236167

申请日：2018-12-28

申请人： Micron Technology, Inc.

发明人： Hyunsuk Chun ,  Sheng Wei Yang ,  Shams U. Arifeen

IPC分类号： H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/768 ,  H01L23/498

摘要： Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

公开(公告)号：US20200211983A1

公开(公告)日：2020-07-02

申请号：US16236167

申请日：2018-12-28

申请人： Micron Technology, Inc.

发明人： Hyunsuk Chun ,  Sheng Wei Yang ,  Shams U. Arifeen

IPC分类号： H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L23/498 ,  H01L21/768

摘要： Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

公开(公告)号：US20240203827A1

公开(公告)日：2024-06-20

申请号：US18416579

申请日：2024-01-18

申请人： Micron Technology, Inc.

发明人： Xiaopeng Qu ,  Hyunsuk Chun ,  Eiichi Nakano

IPC分类号： H01L23/473 ,  H01L21/48 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/4735 ,  H01L21/4871 ,  H01L23/3672 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50

摘要： Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.