公开(公告)号：US10256406B2

公开(公告)日：2019-04-09

申请号：US15155618

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

公开(公告)号：US09362418B2

公开(公告)日：2016-06-07

申请号：US14606415

申请日：2015-01-27

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  David H. Wells ,  Tuman E. Allen

IPC: H01L29/792 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/51 ,  H01L29/66 ,  H01L27/112 ,  H01L21/84 ,  H01L27/102 ,  H01L29/788 ,  H01L27/115 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Abstract translation: 半导体结构包括与下面的衬底间隔开的半导体材料的主体。 物体可以通过介电材料，开放体积和导电材料中的至少一种与基底物理分离。 这些主体可以由一个或多个导电结构电耦合，其可以用作互连结构以电耦合存储器件的部件。 通过在主体之间提供隔离，半导体结构提供常规SOI衬底（例如，高速度，低功率，增加的器件密度和隔离）的性质，同时显着减少与这种SOI衬底相关联的制造动作和成本。 另外，本公开的半导体结构由于通过中间介电材料隔离物体而提供减小的寄生耦合和电流泄漏。

公开(公告)号：US08987108B2

公开(公告)日：2015-03-24

申请号：US14176780

申请日：2014-02-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  David H. Wells ,  Tuman E. Allen

IPC: H01L21/762 ,  H01L21/84 ,  H01L29/66 ,  H01L27/102 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Abstract translation: 半导体结构包括与下面的衬底间隔开的半导体材料的主体。 物体可以通过介电材料，开放体积和导电材料中的至少一种与基底物理分离。 这些主体可以由一个或多个导电结构电耦合，其可以用作互连结构以电耦合存储器件的部件。 通过在主体之间提供隔离，半导体结构提供常规SOI衬底（例如，高速度，低功率，增加的器件密度和隔离）的性质，同时显着减少与这种SOI衬底相关联的制造动作和成本。 另外，本公开的半导体结构由于通过中间介电材料隔离物体而提供减小的寄生耦合和电流泄漏。

公开(公告)号：US20140206175A1

公开(公告)日：2014-07-24

申请号：US14176780

申请日：2014-02-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  David H. Wells ,  Tuman E. Allen

IPC: H01L21/762

CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Abstract translation: 半导体结构包括与下面的衬底间隔开的半导体材料的主体。 物体可以通过介电材料，开放体积和导电材料中的至少一种与基底物理分离。 这些主体可以由一个或多个导电结构电耦合，其可以用作互连结构以电耦合存储器件的部件。 通过在主体之间提供隔离，半导体结构提供常规SOI衬底（例如，高速度，低功率，增加的器件密度和隔离）的性质，同时显着减少与这种SOI衬底相关联的制造动作和成本。 另外，本公开的半导体结构由于通过中间介电材料隔离物体而提供减小的寄生耦合和电流泄漏。