公开(公告)号：US20130250701A1

公开(公告)日：2013-09-26

申请号：US13894069

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/2272

Abstract: Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

Abstract translation: 用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。 一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。 在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。 定时电路还包括写平均触发器（FF）电路和写数据寄存器。 一种这样的方法包括产生和锁定内部写命令。 锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。 内部写入命令通过内部写命令路径进行传播。 写数据被捕获，并且内部写命令响应于写时钟信号而被锁存。 捕获的写入数据被释放以写入存储器。

公开(公告)号：US09607668B2

公开(公告)日：2017-03-28

申请号：US14473574

申请日：2014-08-29

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/12 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/1048

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

公开(公告)号：US20140333357A1

公开(公告)日：2014-11-13

申请号：US14445924

申请日：2014-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Jason Brown ,  Tyler J. Gomm

IPC: H03L7/08 ,  H03K5/159

CPC classification number: H03L7/0802 ,  G11C7/04 ,  G11C7/222 ,  H03K5/159 ,  H03L7/08 ,  H03L7/0816

Abstract: Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.

Abstract translation: 公开延迟模型的电路，装置和方法。 在一个这样的示例电路中，第一延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第一输出信号。 第二延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第二输出信号。 比较电路耦合到第一和第二延迟模型电路。 比较电路被配置为比较来自第一延迟模型电路的第三信号和来自第二延迟模型电路的第四信号，并且响应于提供调整信号以调整第二延迟模型电路的延迟。

公开(公告)号：US08760961B2

公开(公告)日：2014-06-24

申请号：US13894069

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Jason Brown

IPC: G11C8/00

CPC classification number: G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/2272

Abstract: Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

Abstract translation: 用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。 一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。 在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。 定时电路还包括写平均触发器（FF）电路和写数据寄存器。 一种这样的方法包括产生和锁定内部写命令。 锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。 内部写入命令通过内部写命令路径进行传播。 写数据被捕获，并且内部写命令响应于写时钟信号而被锁存。 捕获的写入数据被释放以写入存储器。