公开(公告)号：US09905279B2

公开(公告)日：2018-02-27

申请号：US15436513

申请日：2017-02-17

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/12 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/1048

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

公开(公告)号：US20170162240A1

公开(公告)日：2017-06-08

申请号：US15436513

申请日：2017-02-17

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/12 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/1048

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

公开(公告)号：US20130329503A1

公开(公告)日：2013-12-12

申请号：US13965918

申请日：2013-08-13

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  H03L7/00

Abstract: Command paths, apparatuses, memories, and methods for providing an internal command to a data path are disclosed. In an example method, a command is received and propagated through a command path to provide an internal command. Further included in the method is determining a difference between a latency value and a path delay difference, the path delay difference representing a modeled path delay difference between the command path and the data path measured in terms of a number of clock periods. The propagation of the command through the command path to the data path is delayed by a delay based at least in part on the difference between the latency value and the path delay difference. The internal command is provided to the data path responsive to an internal clock signal.

Abstract translation: 公开了用于向数据路径提供内部命令的命令路径，装置，存储器和方法。 在一个示例方法中，通过命令路径接收和传播命令以提供内部命令。 该方法还包括确定等待时间值和路径延迟差之间的差异，路径延迟差表示按照时钟周期数来测量的命令路径和数据路径之间的建模路径延迟差。 命令通过命令路径传播到数据路径的延迟至少部分地基于延迟值和路径延迟差之间的差异延迟延迟。 内部命令根据内部时钟信号提供给数据通路。

公开(公告)号：US09929064B2

公开(公告)日：2018-03-27

申请号：US14877360

申请日：2015-10-07

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Jason M. Brown

IPC: H01L21/66 ,  G01R31/3185 ,  H01L23/48 ,  G01R31/317

CPC classification number: H01L22/22 ,  G01R31/31717 ,  G01R31/318513 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections. Other apparatuses and methods are disclosed.

公开(公告)号：US08644096B2

公开(公告)日：2014-02-04

申请号：US13965918

申请日：2013-08-13

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/00

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  H03L7/00

Abstract: Command paths, apparatuses, memories, and methods for providing an internal command to a data path are disclosed. In an example method, a command is received and propagated through a command path to provide an internal command. Further included in the method is determining a difference between a latency value and a path delay difference, the path delay difference representing a modeled path delay difference between the command path and the data path measured in terms of a number of clock periods. The propagation of the command through the command path to the data path is delayed by a delay based at least in part on the difference between the latency value and the path delay difference. The internal command is provided to the data path responsive to an internal clock signal.

Abstract translation: 公开了用于向数据路径提供内部命令的命令路径，装置，存储器和方法。 在一个示例方法中，通过命令路径接收和传播命令以提供内部命令。 该方法还包括确定等待时间值和路径延迟差之间的差异，路径延迟差表示按照时钟周期数来测量的命令路径和数据路径之间的建模路径延迟差。 命令通过命令路径传播到数据路径的延迟至少部分地基于延迟值和路径延迟差之间的差异延迟延迟。 内部命令根据内部时钟信号提供给数据通路。

公开(公告)号：US20240070093A1

公开(公告)日：2024-02-29

申请号：US17823443

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Jason McBride Brown ,  Venkatraghavan Bringivijayaraghavan ,  Vijayakrishna J. Vankayala

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1621 ,  G06F13/1689 ,  G06F13/4068

Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.

公开(公告)号：US20140071777A1

公开(公告)日：2014-03-13

申请号：US14077798

申请日：2013-11-12

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1048

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

Abstract translation: 公开了用于电荷共享的系统，电路和方法。 在一个这样的示例系统中，第一线被配置为被驱动到表示要放置在第一线上的数据的第一电压，然后预充电到第一预充电电压。 第二线被配置为被驱动到表示要放置在第二线上的数据的第二电压，然后预充电到第二预充电电压。 电荷共享装置耦合在第一线和第二线之间。 电荷共享装置被配置为在将第一和第二线路驱动到表示要放置在相应线路上的数据的相应第一和第二电压之后，选择性地允许来自第一线路的电荷流到第二线路。

公开(公告)号：US20160027706A1

公开(公告)日：2016-01-28

申请号：US14877360

申请日：2015-10-07

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Jason M. Brown

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L22/22 ,  G01R31/31717 ,  G01R31/318513 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.

公开(公告)号：US20140369146A1

公开(公告)日：2014-12-18

申请号：US14473574

申请日：2014-08-29

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan

IPC: G11C7/12 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/1048

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

公开(公告)号：US20140298146A1

公开(公告)日：2014-10-02

申请号：US14307249

申请日：2014-06-17

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Venkatraghavan Bringivijayaraghavan

IPC: G06F11/18

CPC classification number: G06F11/183 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C2207/107 ,  H04L25/028 ,  H04L25/4915

Abstract: Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in a device for further analysis in the device based on the results of the majority bit detection. In an embodiment, such further processing in a memory device after majority bit detection may include data bit inversion prior to outputting the data from the memory device.

Abstract translation: 可以在各种应用中使用包括检测多个数据位中的大多数值的电子设备的电子设备和制造。 实施例包括应用多数位检测来处理设备中的数据位，以便基于多数位检测的结果在设备中进一步分析。 在一个实施例中，在大多数位检测之后的存储器件中的这种进一步处理可以包括在从存储器件输出数据之前的数据位反转。