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    Memory arrays
    12.
    发明授权
    Memory arrays 有权
    内存阵列

    公开(公告)号：US09559163B2

    公开(公告)日：2017-01-31

    申请号：US14480454

    申请日：2014-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Zailong Bian ,  Janos Fucsko

    IPC: H01L31/113 ,  H01L29/06 ,  H01L21/764 ,  H01L27/115 ,  H01L27/105 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

    Abstract translation: 本发明包括具有沟槽隔离区域的半导体结构。 沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。 电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。 沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。 本发明还包括形成半导体结构的方法。

    Memory Arrays
    13.
    发明申请
    Memory Arrays 有权
    记忆阵列

    公开(公告)号：US20140374833A1

    公开(公告)日：2014-12-25

    申请号：US14480454

    申请日：2014-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Zailong Bian ,  Janos Fucsko

    IPC: H01L29/06 ,  H01L27/105

    CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

    Abstract translation: 本发明包括具有沟槽隔离区域的半导体结构。 沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。 电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。 沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。 本发明还包括形成半导体结构的方法。

    Methods of Fabricating Integrated Circuitry
    19.
    发明申请
    Methods of Fabricating Integrated Circuitry 有权
    集成电路制作方法

    公开(公告)号：US20160126181A1

    公开(公告)日：2016-05-05

    申请号：US14992280

    申请日：2016-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Zailong Bian

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.

    Abstract translation: 一种制造集成电路的方法包括形成第一导线。 选择性地相对于任何暴露的非导电材料将第一元素钨直接沉积在第一导电线的正面外表面上。 电介质材料在第一导电线的正上方形成，并且通孔形成在第一导电线的第一导电层的第一钨沉积位置处的导电材料。 第二元素钨被非选择性地沉积到通孔内并电耦合到第一导电线。 第二导线形成在通孔内的第二钨的高度外侧并电耦合。

    Methods Of Fabricating Integrated Circuitry
    20.
    发明申请
    Methods Of Fabricating Integrated Circuitry 审中-公开
    制作集成电路的方法

    公开(公告)号：US20140248767A1

    公开(公告)日：2014-09-04

    申请号：US13782213

    申请日：2013-03-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zailong Bian

    IPC: H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.

    Abstract translation: 一种制造集成电路的方法包括形成第一导线。 选择性地相对于任何暴露的非导电材料将第一元素钨直接沉积在第一导电线的正面外表面上。 电介质材料在第一导电线的正上方形成，并且通孔形成在第一导电线的第一导电层的第一钨沉积位置处的导电材料。 第二元素钨被非选择性地沉积到通孔内并电耦合到第一导电线。 第二导线形成在通孔内的第二钨的高度外侧并电耦合。

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