公开(公告)号：US07124389B2

公开(公告)日：2006-10-17

申请号：US10848102

申请日：2004-05-17

申请人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

发明人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.

公开(公告)号：US06904572B2

公开(公告)日：2005-06-07

申请号：US10378731

申请日：2003-03-03

申请人： Mutsunori Igarashi

发明人： Mutsunori Igarashi

IPC分类号： G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/505

摘要： A computer-implemented method for designing a semiconductor integrated circuit, which optimizes the propagation delay of a path from a signal input terminal (source) to a signal output terminal (sink) on the same net, includes: calculating the ratio of the total sum of a gate input load capacitance to the wiring capacitance of the path from the source to the sink as a process variation sensitivity relating to the capacitance component of the path to be designed from the source to the sink, based on a circuit design information of a gate level of the semiconductor integrated circuit to be designed; and optimizing the process variation sensitivity relating to the capacitance component of each path in order that the process variation sensitivities relating to the capacitance components of all the paths are smaller than a reference value.

摘要翻译： 一种用于设计半导体集成电路的计算机实现的方法，其优化从同一网络上的信号输入端（源）到信号输出端（汇）的路径的传播延迟，包括：计算总和 基于从源到宿的电路设计信息，从源到宿的路径的布线电容的栅极输入负载电容作为与从源到宿设计的路径的电容分量有关的过程变化灵敏度 要设计的半导体集成电路的栅极电平; 并且优化与每个路径的电容分量相关的过程变化灵敏度，以使与所有路径的电容分量相关的过程变化灵敏度小于参考值。

公开(公告)号：US06779167B2

公开(公告)日：2004-08-17

申请号：US10133953

申请日：2002-04-26

申请人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

发明人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

IPC分类号： G06F1750

CPC分类号： G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.

摘要翻译： 提供了一种自动布线图案布局方法。 利用该方法，产生具有宽度W并沿第一方向延伸的第一布线图案，并且以宽度W产生第二布线图案并且沿垂直于第一布线图案的方向延伸，使得其端部结束 在第一布线图案的端部。 此外，通过将第一或第二布线图案中的任一个的端部以直角弯曲而产生重叠区域以产生L形延伸部并且覆盖第一和第二布线图案，并且形成矩形VIA图案 在重叠区域产生。

公开(公告)号：US5986961A

公开(公告)日：1999-11-16

申请号：US955530

申请日：1997-10-22

申请人： Mutsunori Igarashi

发明人： Mutsunori Igarashi

IPC分类号： H01L21/822 ,  G11C5/02 ,  G11C5/14 ,  H01L21/82 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C5/025 ,  G11C5/14

摘要： A semiconductor integrated circuit of a low power consumption type has modules (1) to which various supply voltages are provided. In each module (1), cells (3) are grouped into cell rows or cell columns. Only one of a wire (7) of a high supply voltage and a wire (5) of a low supply voltage is formed on each cell row or cell column in the module (1). Various supply voltages are provided into the target cell (3) through the electrical wires (5, 7).

摘要翻译： 低功耗型的半导体集成电路具有提供各种电源电压的模块（1）。 在每个模块（1）中，单元格（3）被分组成单元行或单元列。 在模块（1）中的每个单元行或单元列上仅形成高电源线（7）中的一个和低电源电压的导线（5）中的一个。 通过电线（5,7）向目标电池（3）提供各种电源电压。

公开(公告)号：US5397749A

公开(公告)日：1995-03-14

申请号：US910525

申请日：1992-07-08

申请人： Mutsunori Igarashi

发明人： Mutsunori Igarashi

IPC分类号： H01L21/82 ,  G06F17/50 ,  H01L27/02 ,  H01L27/118 ,  H01L21/00

CPC分类号： H01L27/0207

摘要： A method for arranging a group of logical cells through which a signal is transmitted within an allowable delay time, consisting of the steps of determining signal lines interconnecting the logical cells of the equipotential net, defining a critical path consisting of the signal lines of all the equipotential nets, classifying the logical cells positioned between the equipotential nets as path core cells and classifying the other logical cells as path branch cells, positioning the path core cells to shorten the length of a main signal route passing through the path core cells, positioning the path branch cells to shorten the distance between the main signal route and the path branch cell for each equipotential net, and decreasing the delay time of the critical path formed by the replaced path core cells and the replaced path branch cells within the allowable delay time.

摘要翻译： 一种用于布置在允许的延迟时间内通过其发送信号的一组逻辑单元的方法，包括确定连接等电位网络的逻辑单元的信号线的步骤，所述信号线定义了由所有这些信号线的信号线组成的关键路径 等位网络，将位于等电位网之间的逻辑单元分类为路径核心小区，并将其他逻辑单元分类为路径分支小区，定位路径核心单元以缩短通过路径核心小区的主信号路由的长度， 路径分支小区，以缩短每个等势网的主信号路径和路径分支小区之间的距离，并且将由替换的路径核心小区和替换的路径分支小区形成的关键路径的延迟时间减少到可允许的延迟时间内。

公开(公告)号：US5224057A

公开(公告)日：1993-06-29

申请号：US959468

申请日：1992-10-09

申请人： Mutsunori Igarashi ,  Kaori Kora

发明人： Mutsunori Igarashi ,  Kaori Kora

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： An arrangement method for logic cells in a semiconductor IC device, in which a plurality of logic cells are arranged on a semiconductor chip and wiring is performed between the logic cells so as to realize a desired circuit, comprises the steps of developing the logic cell informations to be arranged on the chip and already-arranged cell and wiring informations into connection pins and inhibited areas for wiring, converting the inhibited areas for wiring into equivalent pins so as to treat the inhibited areas for wiring equivalently with respect to the connection pins, and imaginarily dividing the chip into lattices and subsequently uniforming a ratio of a sum of the numbers of the connection pins and the equivalent pins to a region capable of arrangement in each lattice, whereby a position of each logic cell is determined.

摘要翻译： 一种在半导体IC器件中的逻辑单元的布置方法，其中多个逻辑单元布置在半导体芯片上并且在逻辑单元之间执行布线以实现期望的电路，包括以下步骤：开发逻辑单元信息 布置在芯片上并且已经布置的单元和布线信息到连接引脚和禁止的布线区域中，将布线的禁止区域转换成等效的引脚，以便相对于连接引脚等效地处理禁止的布线等效的区域，以及 将芯片划分成晶格，然后将连接引脚和等效引脚的数量之和的比例均匀化为能够在每个晶格中布置的区域，从而确定每个逻辑单元的位置。

公开(公告)号：US07539952B2

公开(公告)日：2009-05-26

申请号：US11522049

申请日：2006-09-14

申请人： Atsushi Watanabe ,  Mutsunori Igarashi

发明人： Atsushi Watanabe ,  Mutsunori Igarashi

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/00 ,  G03F1/36 ,  H01L27/11803

摘要： A reticle set includes a first reticle including a first wiring pattern having a first termination pattern; a second reticle including a plurality of via patterns; and a third reticle including a second wiring pattern having a second termination pattern and a second line pattern connected to an end of the second termination pattern.

摘要翻译： 标线组包括：第一掩模版，其包括具有第一端接图案的第一布线图案; 包括多个通孔图案的第二掩模版; 以及第三掩模版，其包括具有第二端接图案的第二布线图案和连接到所述第二端接图案的端部的第二线图案。

公开(公告)号：US07064691B2

公开(公告)日：2006-06-20

申请号：US10213065

申请日：2002-08-07

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03M7/20 ,  H04B1/38 ,  H04L5/16 ,  H04H7/00

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

摘要翻译： 噪声抑制电路包括内部电路，旁路电容器，第一和第二晶体管。 内部电路具有高低电平端子，低电平端子连接到低电平电源线。 内部电路提供使能和反相使能信号。 第一晶体管具有第一控制电极，一个主电极连接到高电平端子。 第一控制电极被提供有反相使能信号。 旁路电容器连接在第一晶体管的另一个主电极和低电平电源线之间。 第二晶体管连接在第一晶体管的另一个主电极和高电平电源线之间。 第二晶体管具有提供有使能信号的第二控制电极。 内部电路激活时，第二个晶体管不导通。

公开(公告)号：US06792593B2

公开(公告)日：2004-09-14

申请号：US10133683

申请日：2002-04-25

申请人： Makoto Takashima ,  Atsuhiko Ikeuchi ,  Koji Hashimoto ,  Mutsunori Igarashi ,  Masaaki Yamada

发明人： Makoto Takashima ,  Atsuhiko Ikeuchi ,  Koji Hashimoto ,  Mutsunori Igarashi ,  Masaaki Yamada

IPC分类号： G06F1750

CPC分类号： G03F1/36

摘要： In a pattern correction method, design layout data of a pattern designed by an automated layout unit is entered. An environmental profile is determined based on whether or not another graphics pattern exists at the surroundings of each correction target cell included in the entered design layout data. A target cell name is replaced with a prescribed cell name of correction pattern corresponding to the determined environmental profile by referencing a cell replacement table. An OPC correction pattern corresponding to the replaced cell name is imported from a cell library.

摘要翻译： 在图案校正方法中，输入由自动布局单元设计的图案的设计布局数据。 基于在输入的设计布局数据中包括的每个校正目标单元的周围是否存在另一图形模式来确定环境简档。 通过参照小区替换表，将目标小区名称替换为与确定的环境简档对应的校正模式的规定小区名称。 从更换的单元格名称对应的OPC校正模式从单元库导入。

公开(公告)号：US06459331B1

公开(公告)日：2002-10-01

申请号：US09146035

申请日：1998-09-02

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03K500

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

摘要翻译： 噪声抑制电路包括内部电路，旁路电容器，第一和第二晶体管。 内部电路具有高低电平端子，低电平端子连接到低电平电源线。 内部电路提供使能和反相使能信号。 第一晶体管具有第一控制电极，一个主电极连接到高电平端子。 第一控制电极被提供有反相使能信号。 旁路电容器连接在第一晶体管的另一个主电极和低电平电源线之间。 第二晶体管连接在第一晶体管的另一个主电极和高电平电源线之间。 第二晶体管具有提供有使能信号的第二控制电极。 内部电路激活时，第二个晶体管不导通。