公开(公告)号：US06763508B2

公开(公告)日：2004-07-13

申请号：US10122402

申请日：2002-04-12

申请人： Mutsunori Igarashi ,  Takashi Mitsuhashi

发明人： Mutsunori Igarashi ,  Takashi Mitsuhashi

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit configured to register a list expressing an optimum wire terminating process for each via shape of said basic via shape list registered in said library information storage unit; and a central processing control unit configured to refer to the lists respectively registered in said library information storage unit and said technology database storage unit, select an optimum line processing, and execute a line design.

公开(公告)号：US06436804B1

公开(公告)日：2002-08-20

申请号：US09810579

申请日：2001-03-19

申请人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

发明人： Mutsunori Igarashi ,  Takashi Mitsuhashi ,  Masami Murakata ,  Masaaki Yamada ,  Fumihiro Minami ,  Toshihiro Akiyama ,  Takahiro Aoki

IPC分类号： H01L2144

摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost. The present invention forms an X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the(m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring grid, and also wiring widths of {square root over (2)} times of that of wiring in the reference wiring layer.

公开(公告)号：US06097043A

公开(公告)日：2000-08-01

申请号：US996998

申请日：1997-12-23

申请人： Mutsunori Igarashi ,  Hiroshi Tanaka ,  Kimiyoshi Usami ,  Takashi Ishikawa ,  Masahiro Kanazawa ,  Chiharu Mizuno

发明人： Mutsunori Igarashi ,  Hiroshi Tanaka ,  Kimiyoshi Usami ,  Takashi Ishikawa ,  Masahiro Kanazawa ,  Chiharu Mizuno

IPC分类号： H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L23/50

CPC分类号： H01L23/5286 ,  H01L2924/0002

摘要： A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).

摘要翻译： 一种半导体集成电路，提供多个电源电压的供给方法，以及用于存储提供多个电压的供给方法的程序的记录介质，由此提供提供多个电源电压的第一单元（步骤S1） ，将提取的单元分成组（步骤S2），根据组的数量添加并排列用于电压供给的单元（步骤S3），并且用于供电的单元连接到用于提供多个单元的第一单元 的电压通过网络供电（步骤S4）。

公开(公告)号：US07230554B2

公开(公告)日：2007-06-12

申请号：US11411143

申请日：2006-04-26

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03M1/00

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent so as to make the numbers of “0” and “1” in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.

公开(公告)号：US20070011638A1

公开(公告)日：2007-01-11

申请号：US11522049

申请日：2006-09-14

申请人： Atsushi Watanabe ,  Mutsunori Igarashi

发明人： Atsushi Watanabe ,  Mutsunori Igarashi

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/00 ,  G03F1/36 ,  H01L27/11803

摘要： A reticle set includes a first reticle including a first wiring pattern having a first termination pattern; a second reticle including a plurality of via patterns; and a third reticle including a second wiring pattern having a second termination pattern and a second line pattern connected to an end of the second termination pattern.

摘要翻译： 标线组包括：第一掩模版，其包括具有第一端接图案的第一布线图案; 包括多个通孔图案的第二掩模版; 以及第三掩模版，其包括具有第二端接图案的第二布线图案和连接到所述第二端接图案的端部的第二线图案。

公开(公告)号：US06813756B2

公开(公告)日：2004-11-02

申请号：US10279403

申请日：2002-10-24

申请人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

发明人： Mutsunori Igarashi ,  Masami Murakata ,  Takashi Mitsuhashi ,  Masaaki Yamada ,  Fumihiro Minami ,  Takashi Ishioka

IPC分类号： G06F1750

CPC分类号： H01L23/528 ,  G06F1/10 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

摘要： With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

摘要翻译： 利用自动布局方法，在规定的方向上产生具有第一线宽的第一线。 产生具有第二线宽并相对于第一线以倾斜角延伸的第二线，使得第二线终止于第一线的端部处，具有重叠区域。 根据重叠区域的形状，从数据库读出一个或多个VIA图案。 VIA图案被放置在重叠区域中，使得VIA图案之一位于第一和第二行的中心线的交叉处。 VIA模式是平行四边形的组合，包括正方形和矩形。

公开(公告)号：US07124389B2

公开(公告)日：2006-10-17

申请号：US10848102

申请日：2004-05-17

申请人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

发明人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.

公开(公告)号：US06904572B2

公开(公告)日：2005-06-07

申请号：US10378731

申请日：2003-03-03

申请人： Mutsunori Igarashi

发明人： Mutsunori Igarashi

IPC分类号： G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/505

摘要： A computer-implemented method for designing a semiconductor integrated circuit, which optimizes the propagation delay of a path from a signal input terminal (source) to a signal output terminal (sink) on the same net, includes: calculating the ratio of the total sum of a gate input load capacitance to the wiring capacitance of the path from the source to the sink as a process variation sensitivity relating to the capacitance component of the path to be designed from the source to the sink, based on a circuit design information of a gate level of the semiconductor integrated circuit to be designed; and optimizing the process variation sensitivity relating to the capacitance component of each path in order that the process variation sensitivities relating to the capacitance components of all the paths are smaller than a reference value.

摘要翻译： 一种用于设计半导体集成电路的计算机实现的方法，其优化从同一网络上的信号输入端（源）到信号输出端（汇）的路径的传播延迟，包括：计算总和 基于从源到宿的电路设计信息，从源到宿的路径的布线电容的栅极输入负载电容作为与从源到宿设计的路径的电容分量有关的过程变化灵敏度 要设计的半导体集成电路的栅极电平; 并且优化与每个路径的电容分量相关的过程变化灵敏度，以使与所有路径的电容分量相关的过程变化灵敏度小于参考值。

公开(公告)号：US06779167B2

公开(公告)日：2004-08-17

申请号：US10133953

申请日：2002-04-26

申请人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

发明人： Mutsunori Igarashi ,  Masaaki Yamada ,  Koji Hashimoto ,  Makoto Takashima ,  Atsuhiko Ikeuchi

IPC分类号： G06F1750

CPC分类号： G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.

摘要翻译： 提供了一种自动布线图案布局方法。 利用该方法，产生具有宽度W并沿第一方向延伸的第一布线图案，并且以宽度W产生第二布线图案并且沿垂直于第一布线图案的方向延伸，使得其端部结束 在第一布线图案的端部。 此外，通过将第一或第二布线图案中的任一个的端部以直角弯曲而产生重叠区域以产生L形延伸部并且覆盖第一和第二布线图案，并且形成矩形VIA图案 在重叠区域产生。

公开(公告)号：US5986961A

公开(公告)日：1999-11-16

申请号：US955530

申请日：1997-10-22

申请人： Mutsunori Igarashi

发明人： Mutsunori Igarashi

IPC分类号： H01L21/822 ,  G11C5/02 ,  G11C5/14 ,  H01L21/82 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C5/025 ,  G11C5/14

摘要： A semiconductor integrated circuit of a low power consumption type has modules (1) to which various supply voltages are provided. In each module (1), cells (3) are grouped into cell rows or cell columns. Only one of a wire (7) of a high supply voltage and a wire (5) of a low supply voltage is formed on each cell row or cell column in the module (1). Various supply voltages are provided into the target cell (3) through the electrical wires (5, 7).

摘要翻译： 低功耗型的半导体集成电路具有提供各种电源电压的模块（1）。 在每个模块（1）中，单元格（3）被分组成单元行或单元列。 在模块（1）中的每个单元行或单元列上仅形成高电源线（7）中的一个和低电源电压的导线（5）中的一个。 通过电线（5,7）向目标电池（3）提供各种电源电压。