公开(公告)号：US20190051633A1

公开(公告)日：2019-02-14

申请号：US15675214

申请日：2017-08-11

Applicant: Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/29 ,  H01L23/528

Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

公开(公告)号：US20200312766A1

公开(公告)日：2020-10-01

申请号：US16367731

申请日：2019-03-28

Applicant: Milind S. Bhagavat ,  Rahul Agarwal ,  Chia-Hao Cheng

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Chia-Hao Cheng

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

公开(公告)号：US20200294914A1

公开(公告)日：2020-09-17

申请号：US16351728

申请日：2019-03-13

Applicant: Rahul Agarwal ,  Chia-Hao Cheng ,  Milind S. Bhagavat

Inventor： Rahul Agarwal ,  Chia-Hao Cheng ,  Milind S. Bhagavat

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

公开(公告)号：US20190333851A1

公开(公告)日：2019-10-31

申请号：US15965576

申请日：2018-04-27

Applicant: Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.

公开(公告)号：US20190326221A1

公开(公告)日：2019-10-24

申请号：US15961222

申请日：2018-04-24

Applicant: Milind S. Bhagavat ,  Rahul Agarwal

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/18

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US10312221B1

公开(公告)日：2019-06-04

申请号：US15844575

申请日：2017-12-17

Applicant: Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

Inventor： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC: H01L23/52 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.

公开(公告)号：US20190164936A1

公开(公告)日：2019-05-30

申请号：US15826054

申请日：2017-11-29

Applicant: Rahul Agarwal ,  Milind S. Bhagavat

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.

公开(公告)号：US10672712B2

公开(公告)日：2020-06-02

申请号：US16048826

申请日：2018-07-30

Applicant: Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L25/16 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

公开(公告)号：US20190067152A1

公开(公告)日：2019-02-28

申请号：US15686558

申请日：2017-08-25

Applicant: John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/065 ,  H01L25/00

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US07601049B2

公开(公告)日：2009-10-13

申请号：US11617433

申请日：2006-12-28

Applicant: Sumeet S. Bhagavat ,  Milind S. Bhagavat ,  Roland R. Vandamme ,  Tomomi Komura

Inventor： Sumeet S. Bhagavat ,  Milind S. Bhagavat ,  Roland R. Vandamme ,  Tomomi Komura

IPC: B24B49/00

CPC classification number: B24B37/28 ,  B24B7/228 ,  B24B49/02

Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.

Abstract translation: 双面研磨机包括一对砂轮和一对静压垫，其可操作以保持平坦工件（例如，半导体晶片），使得工件的一部分位于砂轮之间并且部分工件位于静水压 垫 至少一个传感器测量工件和相应传感器之间的距离，用于评估工件的纳米拓扑学。 在本发明的方法中，在研磨期间测量与工件的距离，并用于评估工件的纳米拓扑学。 例如，可以使用传感器数据来执行工件的有限元结构分析以导出至少一个边界条件。 纳米技术评估可以在从研磨机上取出工件之前开始，提供快速的纳米拓扑反馈。 可以使用空间滤波器来进一步处理后预测工件的可能纳米拓扑。