公开(公告)号：US10431517B2

公开(公告)日：2019-10-01

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20190067152A1

公开(公告)日：2019-02-28

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L25/00

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20070229147A1

公开(公告)日：2007-10-04

申请号：US11395475

申请日：2006-03-30

申请人： Bruce Doyle ,  Manish Kumar ,  John Wuu ,  Samuel Naffziger

发明人： Bruce Doyle ,  Manish Kumar ,  John Wuu ,  Samuel Naffziger

IPC分类号： G05F1/10

CPC分类号： G05F1/46

摘要： For one disclosed embodiment, a supply voltage regulator is to control voltage at a first supply node for a circuit. The supply voltage regulator includes one or more first devices to couple the first supply node to a second supply node when the circuit is in a predetermined operational state and includes an error sensor to control the one or more first devices. The supply voltage regulator includes one or more second devices to couple the first supply node to a third supply node when the circuit is in the predetermined operational state. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，电源电压调节器用于控制电路的第一供电节点处的电压。 电源电压调节器包括一个或多个第一器件，用于当电路处于预定操作状态时将第一电源节点耦合到第二电源节点，并且包括用于控制一个或多个第一器件的误差传感器。 电源稳压器包括一个或多个第二设备，用于当电路处于预定操作状态时将第一供电节点耦合到第三供电节点。 还公开了其他实施例。

公开(公告)号：US07724567B2

公开(公告)日：2010-05-25

申请号：US12167821

申请日：2008-07-03

申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

IPC分类号： G11C11/36

CPC分类号： G11C15/04 ,  G06F12/0864 ,  G06F12/0895 ,  G11C11/39

摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

摘要翻译： 内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。 第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平 匹配检测操作。 内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

公开(公告)号：US20100002482A1

公开(公告)日：2010-01-07

申请号：US12167823

申请日：2008-07-03

申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C11/39

摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

摘要翻译： 内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。 第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平 匹配检测操作。 内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

公开(公告)号：US20060142962A1

公开(公告)日：2006-06-29

申请号：US11024086

申请日：2004-12-28

申请人： Donald Weiss ,  Richard Woodruff ,  John Wuu

发明人： Donald Weiss ,  Richard Woodruff ,  John Wuu

IPC分类号： G01R19/00

CPC分类号： G11C29/028 ,  G11C11/41 ,  G11C11/419 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/5006

摘要： According to at least one embodiment, a method comprises measuring drive current of a reference memory cell of a circuit, and determining, based on the measured drive current of the reference memory cell, a drive current to be supplied to a calibration memory cell of the circuit to mimic a defective memory cell. The method further comprises supplying the determined drive current to the calibration memory cell, and using the calibration memory cell to determine strength of a weak write to be utilized by a weak write test for detecting defective memory cells.

摘要翻译： 根据至少一个实施例，一种方法包括测量电路的参考存储单元的驱动电流，以及基于所测量的参考存储单元的驱动电流来确定要提供给该参考存储单元的校准存储单元的驱动电流 电路以模拟有缺陷的存储器单元。 该方法还包括将确定的驱动电流提供给校准存储单元，以及使用校准存储单元来确定弱写入测试用于检测有缺陷的存储器单元的弱写入的强度。

公开(公告)号：US20050050400A1

公开(公告)日：2005-03-03

申请号：US10653020

申请日：2003-08-30

申请人： John Wuu ,  Donald Weiss ,  Matthew Unangst

发明人： John Wuu ,  Donald Weiss ,  Matthew Unangst

IPC分类号： G06F11/00

CPC分类号： G11C29/4401 ,  G11C29/802 ,  G11C29/848

摘要： A computer system is disclosed that includes a memory, a memory defect map, and a shift encoder. The memory includes a plurality of bits and a plurality of input/output ports for accessing the plurality of bits. The memory defect map specifies positions of defective ones of the plurality of bits. The shift encoder encodes positions of defective ones of the plurality of bits in a shift encoding. The shift encoding includes a shift redundancy record representing positions of transitions between functional bits and defective bits in the memory, and a hints record representing numbers of bits in sets of consecutive defective bits in the memory.

摘要翻译： 公开了一种包括存储器，存储器缺陷映射和移位编码器的计算机系统。 存储器包括用于访问多个位的多个位和多个输入/输出端口。 存储器缺陷图指定多个位中的有缺陷位的位置。 移位编码器在移位编码中编码多个位中的有缺陷位的位置。 移位编码包括表示存储器中的功能位和缺陷位之间的转换位置的移位冗余记录，以及表示存储器中的连续缺陷位集合中的位数的提示记录。

公开(公告)号：US20100146330A1

公开(公告)日：2010-06-10

申请号：US12330012

申请日：2008-12-08

申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

IPC分类号： G06F11/20

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.

摘要翻译： 公开了一种误差校正模块，其中两个比特单元用于以冗余的方式存储一位信息，使得冗余纠错模块可以校正两个比特之一的零星数据错误。

公开(公告)号：US20070079184A1

公开(公告)日：2007-04-05

申请号：US11229084

申请日：2005-09-16

申请人： Donald Weiss ,  John Wuu ,  Charles Morrganti

发明人： Donald Weiss ,  John Wuu ,  Charles Morrganti

IPC分类号： G11C29/00

CPC分类号： G11C29/42 ,  G06F11/1064 ,  G11C29/72

摘要： According to one embodiment, a method comprises detecting a defect in a portion of memory. The method further comprises designating the portion of memory as defective, and avoiding attempts to access the portion of memory designated as defective.

摘要翻译： 根据一个实施例，一种方法包括检测存储器的一部分中的缺陷。 该方法还包括将存储器的该部分指定为有缺陷的，并且避免尝试访问指定为有缺陷的存储器的部分。

公开(公告)号：US06580635B1

公开(公告)日：2003-06-17

申请号：US10133946

申请日：2002-04-25

申请人： Todd W. Mellinger ,  Jonathan E. Lachman ,  John Wuu

发明人： Todd W. Mellinger ,  Jonathan E. Lachman ,  John Wuu

IPC分类号： G11C1140

CPC分类号： G11C7/12 ,  G11C7/18

摘要： During read operations of a column of RAM cells, a bitline is electrically broken into two sections. This reduces the capacitance that needs to be discharged by the RAM cell itself. A buffer is used during the read operation to relay data from one part of the split bitline to the other. A weak pullup path is also provided to hold the non-driven end of the line in a stable condition. During non-read operations, the two sections of bitline are electrically connected.

摘要翻译： 在一列RAM单元的读操作期间，位线被电分为两部分。 这就降低了RAM单元本身需要放电的电容。 在读取操作期间使用缓冲器将数据从分割位线的一部分中继到另一部分。 还提供弱上拉路径以将线的非驱动端保持在稳定状态。 在非读取操作期间，位线的两个部分电连接。