公开(公告)号：US20190067152A1

公开(公告)日：2019-02-28

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L25/00

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US10431517B2

公开(公告)日：2019-10-01

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US10312221B1

公开(公告)日：2019-06-04

申请号：US15844575

申请日：2017-12-17

申请人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

发明人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC分类号： H01L23/52 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.

公开(公告)号：US20190189590A1

公开(公告)日：2019-06-20

申请号：US15844575

申请日：2017-12-17

申请人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

发明人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.

公开(公告)号：US08704370B2

公开(公告)日：2014-04-22

申请号：US13537388

申请日：2012-06-29

申请人： Trent S. Uehling ,  Burton J. Carpenter ,  Brett P. Wilkerson

发明人： Trent S. Uehling ,  Burton J. Carpenter ,  Brett P. Wilkerson

IPC分类号： H01L23/48

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83002 ,  H01L2224/85002 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18165 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package structure includes a package substrate having a top surface and a bottom surface. A semiconductor die having a top surface and a bottom surface. The semiconductor die is mounted to the package substrate. The bottom surface of the semiconductor die is adjacent to the top surface of the package substrate. An air gap is between the bottom surface of the package substrate and the bottom surface of semiconductor die.

摘要翻译： 封装结构包括具有顶表面和底表面的封装衬底。 一种具有顶表面和底表面的半导体管芯。 将半导体管芯安装到封装衬底。 半导体管芯的底表面与封装衬底的顶表面相邻。 在封装衬底的底表面和半导体管芯的底表面之间存在气隙。

公开(公告)号：US20140117554A1

公开(公告)日：2014-05-01

申请号：US13660243

申请日：2012-10-25

申请人： Trent S. Uehling ,  Brett P. Wilkerson

发明人： Trent S. Uehling ,  Brett P. Wilkerson

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only solder pads on the inner portion. The one or more inner solder pads number no more than five. A plurality of outer solder pads are on an outer portion of the second side. An average of areas of the one or more inner solder pads is at least five times an average of areas of the one or more inner solder pads. The plurality of outer solder ball pads are for receiving solder ball balls. The outer portion is spaced from the perimeter of the inner portion. The outer portion and the inner portion are coplanar.

摘要翻译： 封装基板具有安装在第一侧上的管芯。 一个或多个内部焊盘位于第二侧的内部。 内部的周边与模具的周边对准。 一个或多个内部焊盘是内部部分上唯一的焊盘。 一个或多个内部焊盘的数量不超过五个。 多个外部焊盘位于第二侧的外侧部分。 所述一个或多个内部焊盘的平均面积至少为所述一个或多个内部焊盘的面积的平均值的五倍。 多个外焊球焊盘用于接收焊球球。 外部部分与内部部分的周边间隔开。 外部和内部是共面的。

公开(公告)号：US20140001632A1

公开(公告)日：2014-01-02

申请号：US13537388

申请日：2012-06-29

申请人： Trent S. Uehling ,  Burton J. Carpenter ,  Brett P. Wilkerson

发明人： Trent S. Uehling ,  Burton J. Carpenter ,  Brett P. Wilkerson

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83002 ,  H01L2224/85002 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18165 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package structure includes a package substrate having a top surface and a bottom surface. A semiconductor die having a top surface and a bottom surface. The semiconductor die is mounted to the package substrate. The bottom surface of the semiconductor die is adjacent to the top surface of the package substrate. An air gap is between the bottom surface of the package substrate and the bottom surface of semiconductor die.

摘要翻译： 封装结构包括具有顶表面和底表面的封装衬底。 一种具有顶表面和底表面的半导体管芯。 将半导体管芯安装到封装衬底。 半导体管芯的底表面与封装衬底的顶表面相邻。 在封装衬底的底表面和半导体管芯的底表面之间存在气隙。

公开(公告)号：US07276435B1

公开(公告)日：2007-10-02

申请号：US11445657

申请日：2006-06-02

申请人： Scott K. Pozder ,  Kevin J. Hess ,  Ruiqi Tian ,  Edward O. Travis ,  Trent S. Uehling ,  Brett P. Wilkerson ,  Katie C. Yu

发明人： Scott K. Pozder ,  Kevin J. Hess ,  Ruiqi Tian ,  Edward O. Travis ,  Trent S. Uehling ,  Brett P. Wilkerson ,  Katie C. Yu

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014

摘要： An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.

摘要翻译： 集成电路在顶表面上具有金属凸块，当形成金属凸块时，在底层上产生潜在的破坏性应力。 确保底层金属互连层中的最小金属浓度得以实现，以减少破坏作用。 最低金属浓度在角落最高，接下来沿着边界不在拐角处，接下来是内部。 通常在金属凸块下方的互连层中的区域需要比不在凸块下方的相邻区域更多的浓度。 对于远离集成电路表面的金属互连层，需要较小的浓度。 所需的金属浓度通过首先尝试相对简单的解决方案实现。 如果没有效果，则尝试不同的方法，直到达到最小浓度，或直到最后一次尝试。

公开(公告)号：US09324667B2

公开(公告)日：2016-04-26

申请号：US13350098

申请日：2012-01-13

申请人： Trent S. Uehling ,  Lawrence S. Klingbeil ,  Mostafa Vadipour ,  Brett P. Wilkerson ,  Leo M. Higgins, III

发明人： Trent S. Uehling ,  Lawrence S. Klingbeil ,  Mostafa Vadipour ,  Brett P. Wilkerson ,  Leo M. Higgins, III

IPC分类号： H01L21/4763 ,  H01L23/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/05552

摘要： A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

摘要翻译： 一种方法形成到集成电路的焊盘的连接柱。 在接合焊盘上形成种子层。 光刻胶沉积在集成电路上。 在接合焊盘上的光致抗蚀剂中形成开口。 连接柱通过电镀形成在开口中。

公开(公告)号：US07247552B2

公开(公告)日：2007-07-24

申请号：US11033009

申请日：2005-01-11

申请人： Scott K. Pozder ,  Kevin J. Hess ,  Pak K. Leung ,  Edward O. Travis ,  Brett P. Wilkerson ,  David G. Wontor ,  Jie-Hua Zhao

发明人： Scott K. Pozder ,  Kevin J. Hess ,  Pak K. Leung ,  Edward O. Travis ,  Brett P. Wilkerson ,  David G. Wontor ,  Jie-Hua Zhao

IPC分类号： H01L21/4763

CPC分类号： H01L24/10 ,  H01L23/522 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

摘要翻译： 减轻施加到接合焊盘（32）的应力引起的缺陷的问题的技术包括：在实际制造集成电路（10）之前，将互连层（18,22,26）中的虚设金属线（74,76） 以增加互连层的金属密度。 当互连层之间的层间电介质（16,20,24）为低k材料时，这些问题更有可能。 在每个接合垫周围和之下的临界区域或力区域（64）限定了由于与该接合焊盘的接触而可能发生缺陷的区域。 金属密度低于某一百分比的这样关键区域中的任何互连层可能是互连层中缺陷的原因。 在临界区域中具有低于该百分比的金属密度的任何互连层都添加有虚拟金属线。