公开(公告)号：US07742118B2

公开(公告)日：2010-06-22

申请号：US11690563

申请日：2007-03-23

申请人： Jun-Hyung Souk ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

发明人： Jun-Hyung Souk ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

IPC分类号： G02F1/136

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

公开(公告)号：US20080252806A1

公开(公告)日：2008-10-16

申请号：US12141623

申请日：2008-06-18

申请人： Jun-Hyung SOUK ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

发明人： Jun-Hyung SOUK ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

IPC分类号： G02F1/136

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

公开(公告)号：US07403240B2

公开(公告)日：2008-07-22

申请号：US11741470

申请日：2007-04-27

申请人： Jun-Hyung Souk ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

发明人： Jun-Hyung Souk ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

IPC分类号： G02F1/136 ,  G02F1/1335

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

公开(公告)号：US20070200981A1

公开(公告)日：2007-08-30

申请号：US11741470

申请日：2007-04-27

申请人： Jun-Hyung SOUK ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

发明人： Jun-Hyung SOUK ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

IPC分类号： G02F1/1335 ,  G02F1/136

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

公开(公告)号：US20070190706A1

公开(公告)日：2007-08-16

申请号：US11690563

申请日：2007-03-23

申请人： Jun-Hyung Souk ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

发明人： Jun-Hyung Souk ,  Jeong-Young Lee ,  Jong-Soo Yoon ,  Kwon-Young Choi ,  Bum-Ki Baek

IPC分类号： H01L21/84

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

公开(公告)号：US07659625B2

公开(公告)日：2010-02-09

申请号：US12333973

申请日：2008-12-12

申请人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H01L23/48

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US20080090404A1

公开(公告)日：2008-04-17

申请号：US11947204

申请日：2007-11-29

申请人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-kyu Song

发明人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-kyu Song

IPC分类号： H01L21/4763

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US07303987B2

公开(公告)日：2007-12-04

申请号：US10475903

申请日：2002-04-02

申请人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H01L21/4763

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US06977711B2

公开(公告)日：2005-12-20

申请号：US09983878

申请日：2001-10-26

申请人： Sang-Ki Kwak ,  Kwon-Young Choi ,  Young-Jae Tak ,  Myung-Jae Park ,  Woon-Yong Park

发明人： Sang-Ki Kwak ,  Kwon-Young Choi ,  Young-Jae Tak ,  Myung-Jae Park ,  Woon-Yong Park

IPC分类号： G02F1/136 ,  G02F1/13 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  G09F9/35

CPC分类号： G02F1/13458 ,  G02F1/1309 ,  G02F1/1345

摘要： An LCD having a plurality of test pads applied with a common voltage, covered with respective shielding conductor or located sufficiently far from pixels. A gate wire including pluralities of gate lines and test pads disconnected from the gate lines and located near one ends of the gate lines, and a common electrode wire including a plurality of common electrodes and a common electrode pad connected to the common electrode electrodes are formed on a substrate, and covered with a gate insulating film. A data wire and a pixel electrode wire are formed thereon and covered with a passivation film. The passivation film and the gate insulating film have contact holes exposing the test pads and the common electrode pad. A plurality of connecting members which are connected to the test pads and the common electrode pad through the contact holes are formed on the passivation film. Alternatively, the passivation film and the gate insulating layer have contact holes exposing only the common electrode pad, and a plurality of shielding members are provided on the passivation layer to be connected to the common electrode pad and to cover the test pads. Alternatively, the distance between the gate lines and the test pads is equal to or larger than twice the width of the pixel.

摘要翻译： 一种LCD，其具有施加有公共电压的多个测试焊盘，覆盖有相应的屏蔽导体或位于足够远离像素的位置。 一种栅极线，其包括多条栅极线和测试焊盘，与栅极线断开并位于栅极线的一端附近，并且形成包括连接到公共电极电极的多个公共电极和公共电极焊盘的公共电极线 在基板上，并覆盖有栅极绝缘膜。 数据线和像素电极线形成在其上并被钝化膜覆盖。 钝化膜和栅极绝缘膜具有暴露测试焊盘和公共电极焊盘的接触孔。 通过接触孔连接到测试焊盘和公共电极焊盘的多个连接部件形成在钝化膜上。 或者，钝化膜和栅极绝缘层具有仅暴露公共电极焊盘的接触孔，并且在钝化层上设置多个屏蔽构件，以连接到公共电极焊盘并覆盖测试焊盘。 或者，栅极线和测试焊盘之间的距离等于或大于像素宽度的两倍。

公开(公告)号：US20100096176A1

公开(公告)日：2010-04-22

申请号：US12645458

申请日：2009-12-22

申请人： Seung-Taek LIM ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek LIM ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H05K1/11

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。