公开(公告)号：US07659625B2

公开(公告)日：2010-02-09

申请号：US12333973

申请日：2008-12-12

申请人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H01L23/48

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US20080090404A1

公开(公告)日：2008-04-17

申请号：US11947204

申请日：2007-11-29

申请人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-kyu Song

发明人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-kyu Song

IPC分类号： H01L21/4763

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US20100096176A1

公开(公告)日：2010-04-22

申请号：US12645458

申请日：2009-12-22

申请人： Seung-Taek LIM ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek LIM ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H05K1/11

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US20090096105A1

公开(公告)日：2009-04-16

申请号：US12333973

申请日：2008-12-12

申请人： Seung-Taek LIM ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek LIM ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US07303987B2

公开(公告)日：2007-12-04

申请号：US10475903

申请日：2002-04-02

申请人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H01L21/4763

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US07566906B2

公开(公告)日：2009-07-28

申请号：US11958230

申请日：2007-12-17

申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  San-Jin Jeon

发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  San-Jin Jeon

IPC分类号： H01L29/04

CPC分类号： H01L29/41733 ,  H01L27/124

摘要： A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.

摘要翻译： 提供薄膜晶体管阵列面板，其包括基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的多个欧姆接触; 源极和漏极形成在欧姆接触上; 形成在源电极和漏电极上的钝化层，具有露出漏电极的一部分的第一接触孔和露出半导体层的第一部分并且具有与源电极和漏电极的边缘重合的边缘的开口; 以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。

公开(公告)号：US07459323B2

公开(公告)日：2008-12-02

申请号：US11512805

申请日：2006-08-30

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L21/00

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20050082535A1

公开(公告)日：2005-04-21

申请号：US10926719

申请日：2004-08-26

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1368 ,  G03C1/85 ,  G03C5/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US07320906B2

公开(公告)日：2008-01-22

申请号：US10922343

申请日：2004-08-19

申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC分类号： H01L21/84

CPC分类号： H01L29/41733 ,  H01L27/124

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US07119368B2

公开(公告)日：2006-10-10

申请号：US10926719

申请日：2004-08-26

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L31/0376

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.