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公开(公告)号：US06275904B1
公开(公告)日：2001-08-14
申请号：US09053385
申请日：1998-03-31
IPC分类号： G06F1208
CPC分类号： G06F12/0886 , G06F9/30018 , G06F9/30036 , G06F9/30047 , G06F12/0804 , G06F12/0888
摘要： A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
摘要翻译： 一种用于提供高速缓存存储器管理的计算机系统和方法。 计算机系统包括具有多个主存储器地址的主存储器，每个主存储器地址都具有对应的数据条目，以及耦合到主存储器的处理器。 至少一个高速缓存存储器耦合到处理器。 所述至少一个高速缓冲存储器具有具有多个地址的高速缓存目录和具有对应于所述多个地址的多个数据条目的高速缓存控制器。 处理器接收具有操作数地址的指令，并确定操作数地址是否匹配高速缓存目录中的多个地址之一。 如果是这样，则处理器更新对应于匹配地址的高速缓存控制器中的数据条目。 否则，更新与主存储器中的操作数地址相对应的数据条目。
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12.发明授权Method and apparatus for staggering execution of a single packed data instruction using the same circuit 有权用于使用相同电路交错执行单个打包数据指令的方法和装置公开(公告)号：US06687810B2
公开(公告)日：2004-02-03
申请号：US10164976
申请日：2002-06-06
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同的电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。
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13.发明授权公开(公告)号：US06317824B1
公开(公告)日：2001-11-13
申请号：US09049827
申请日：1998-03-27
IPC分类号： G06F1500
CPC分类号： G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30109 , G06F9/30112 , G06F9/3013
摘要： A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. The present invention is useful, for example, when comparisons are performed on floating point data that is typically larger (e.g., 64 bits) than integer data (e.g., 32 bits) and integer operations are preformed based on the result. Because many processors branch based on integer data, the comparison results stored as floating point data must be transferred to an integer register prior to branching. The present invention takes advantage of redundancy of the floating point comparison results to transfer enough data to convey the comparison result to integer registers with a single instruction.
摘要翻译： 一种用于执行移动掩模操作的方法和装置。 本发明提供了一种用于对第一大小和格式的打包数据值执行操作的方法和装置，并且通过消除冗余数据将结果转换成第二大小和格式的数据。 本发明例如在对通常比整数数据（例如，32位）更大（例如，64位））的浮点数据执行比较时是有用的，并且基于结果执行整数运算。 由于许多处理器基于整数数据分支，所以作为浮点数据存储的比较结果必须在分支之前传输到整数寄存器。 本发明利用浮点比较结果的冗余来传送足够的数据，以将比较结果传达给具有单个指令的整数寄存器。
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14.发明授权公开(公告)号：US06694426B2
公开(公告)日：2004-02-17
申请号：US10164774
申请日：2002-06-06
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
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公开(公告)号：US06425073B1
公开(公告)日：2002-07-23
申请号：US09805280
申请日：2001-03-13
IPC分类号： G06F900
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
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公开(公告)号：US07366881B2
公开(公告)日：2008-04-29
申请号：US11103702
申请日：2005-04-11
IPC分类号： G06F9/30
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。
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17.发明授权Staggering execution of a single packed data instruction using the same circuit 失效使用相同电路的单个打包数据指令的交错执行公开(公告)号：US06925553B2
公开(公告)日：2005-08-02
申请号：US10689291
申请日：2003-10-20
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction is then split into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand. The first and second micro instructions are then executed.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收指定操作并分别在第一和第二寄存器中指定第一和第二数据操作数的宏指令。 然后，宏指令被分割成第一微指令和第二微指令，第一微指令指定在包括第一数据操作数的第一部分和第二数据操作数的第一部分的第一对应段上的操作，以及 指定在包括第一数据操作数的第二部分和第二数据操作数的第二部分的第二对应段上的操作的第二微指令。 然后执行第一和第二微指令。
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18.发明授权Method and apparatus for staggering execution of a single packed data instruction using the same circuit 失效用于使用相同电路交错执行单个打包数据指令的方法和装置公开(公告)号：US06230257B1
公开(公告)日：2001-05-08
申请号：US09053004
申请日：1998-03-31
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。
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公开(公告)号：US6115812A
公开(公告)日：2000-09-05
申请号：US53308
申请日：1998-04-01
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method for performing vertical parallel operations on packed data is described. A first set of data operands and a second set of data operands are accessed. Each of these sets of data represents graphical data stored in a first format. The first set of data operands is convereted into a converted set and the second set of data operands is replicated to generate a replicated set. A vertical matrix multiplication is performed on the converted set and the replicated set to generate transformed graphical data.
摘要翻译： 描述了用于对打包数据执行垂直并行操作的装置和方法。 访问第一组数据操作数和第二组数据操作数。 这些数据集中的每一组表示以第一格式存储的图形数据。 第一组数据操作数被转换成转换的集合，并且第二组数据操作数被复制以生成复制集合。 对转换的集合和复制集执行垂直矩阵乘法以生成转换的图形数据。
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公开(公告)号：US09804857B2
公开(公告)日：2017-10-31
申请号：US12971174
申请日：2010-12-17
申请人： Uttam K. Sengupta , Shreekant S. Thakkar , Bruce L. Fleming , Uma M. Gadamsetty , Arvind Mandhani , Shane D. Wall
发明人： Uttam K. Sengupta , Shreekant S. Thakkar , Bruce L. Fleming , Uma M. Gadamsetty , Arvind Mandhani , Shane D. Wall
IPC分类号： G06F9/44 , G06F13/40 , H04B1/3877 , H04B1/3883
CPC分类号： G06F9/4408 , G06F9/441 , G06F13/4081 , H04B1/3877 , H04B1/3883 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a method and apparatus are described for operating a mobile computing device in different modes using different operating systems. An apparatus may comprise, for example, a memory operative to store multiple operating systems, a processor operative to execute the multiple operating systems, an operating system management module operative to select a first operating system when the mobile computing device is in a first mode or a second operating system when the mobile computing device is in a second mode and the mobile computing device is coupled to one or more external devices. Other embodiments are described and claimed.
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