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    Method and apparatus for performing integer operations in response to a result of a floating point operation
    1.
    发明授权
    Method and apparatus for performing integer operations in response to a result of a floating point operation 失效
    响应于浮点运算的结果执行整数运算的方法和装置

    公开(公告)号：US06317824B1

    公开(公告)日：2001-11-13

    申请号：US09049827

    申请日：1998-03-27

    申请人： Shreekant S. Thakkar ,  Wayne H. Scott ,  Patrice Roussel

    发明人： Shreekant S. Thakkar ,  Wayne H. Scott ,  Patrice Roussel

    IPC分类号： G06F1500

    CPC分类号： G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013

    摘要： A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. The present invention is useful, for example, when comparisons are performed on floating point data that is typically larger (e.g., 64 bits) than integer data (e.g., 32 bits) and integer operations are preformed based on the result. Because many processors branch based on integer data, the comparison results stored as floating point data must be transferred to an integer register prior to branching. The present invention takes advantage of redundancy of the floating point comparison results to transfer enough data to convey the comparison result to integer registers with a single instruction.

    摘要翻译： 一种用于执行移动掩模操作的方法和装置。 本发明提供了一种用于对第一大小和格式的打包数据值执行操作的方法和装置，并且通过消除冗余数据将结果转换成第二大小和格式的数据。 本发明例如在对通常比整数数据（例如，32位）更大（例如，64位））的浮点数据执行比较时是有用的，并且基于结果执行整数运算。 由于许多处理器基于整数数据分支，所以作为浮点数据存储的比较结果必须在分支之前传输到整数寄存器。 本发明利用浮点比较结果的冗余来传送足够的数据，以将比较结果传达给具有单个指令的整数寄存器。

    Executing partial-width packed data instructions
    2.
    发明授权
    Executing partial-width packed data instructions 有权
    执行部分宽度打包的数据指令

    公开(公告)号：US06970994B2

    公开(公告)日：2005-11-29

    申请号：US09852217

    申请日：2001-05-08

    申请人： Mohammad Abdallah ,  James Coke ,  Vladimir Pentkovski ,  Patrice Roussel ,  Shreekant S. Thakkar

    发明人： Mohammad Abdallah ,  James Coke ,  Vladimir Pentkovski ,  Patrice Roussel ,  Shreekant S. Thakkar

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318

    CPC分类号： G06F9/3875 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/384 ,  G06F9/3885

    摘要： A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.

    摘要翻译： 讨论了用于执行部分宽度打包数据指令的方法和装置。 处理器可以包括多个寄存器，寄存器重命名单元，解码器和部分宽度执行单元。 寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。 解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。 第一组指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。 相比之下，第二组指令指定仅对数据元素的子集执行的操作。 部分宽度执行单元是执行由第一组或第二组指令指定的操作。

    Method and apparatus for staggering execution of a single packed data instruction using the same circuit
    3.
    发明授权
    Method and apparatus for staggering execution of a single packed data instruction using the same circuit 有权
    用于使用相同电路交错执行单个打包数据指令的方法和装置

    公开(公告)号：US06687810B2

    公开(公告)日：2004-02-03

    申请号：US10164976

    申请日：2002-06-06

    申请人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    发明人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    IPC分类号： G06F1500

    CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3875 ,  G06F9/3885

    摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

    摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同的电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

    Method and apparatus for staggering execution of an instruction
    10.
    发明授权
    Method and apparatus for staggering execution of an instruction 有权

    公开(公告)号：US06425073B1

    公开(公告)日：2002-07-23

    申请号：US09805280

    申请日：2001-03-13

    申请人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    发明人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    IPC分类号： G06F900

    摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.