公开(公告)号：US06847537B2

公开(公告)日：2005-01-25

申请号：US10358550

申请日：2003-02-05

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

摘要翻译： 铁电存储器件包括铁电存储器单元。 铁电存储单元具有至少一个位线和板线。 控制电路在写入操作期间与写入线的激活基本同时地驱动具有写入数据的至少一个位线。 存储器件还可以包括耦合到铁电存储单元的读出放大器，并且控制电路还可以被配置为在读取操作期间与读出放大器的激活基本同时地去激活平板线。

公开(公告)号：US07586774B2

公开(公告)日：2009-09-08

申请号：US11675007

申请日：2007-02-14

申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

公开(公告)号：US07313011B2

公开(公告)日：2007-12-25

申请号：US11491872

申请日：2006-07-24

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

摘要翻译： 铁电存储器件包括铁电存储器单元。 铁电存储单元具有至少一个位线和板线。 控制电路在写入操作期间与写入线的激活基本同时地驱动具有写入数据的至少一个位线。 存储器件还可以包括耦合到铁电存储单元的读出放大器，并且控制电路还可以被配置为在读取操作期间与读出放大器的激活基本同时地去激活平板线。

公开(公告)号：US20070189056A1

公开(公告)日：2007-08-16

申请号：US11675007

申请日：2007-02-14

申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

公开(公告)号：US20060256607A1

公开(公告)日：2006-11-16

申请号：US11491872

申请日：2006-07-24

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

摘要翻译： 铁电存储器件包括铁电存储器单元。 铁电存储单元具有至少一个位线和板线。 控制电路在写入操作期间与写入线的激活基本同时地驱动具有写入数据的至少一个位线。 存储器件还可以包括耦合到铁电存储单元的读出放大器，并且控制电路还可以被配置为在读取操作期间与读出放大器的激活基本同时地去激活平板线。

公开(公告)号：US20050117383A1

公开(公告)日：2005-06-02

申请号：US11029616

申请日：2005-01-05

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

公开(公告)号：US08467244B2

公开(公告)日：2013-06-18

申请号：US12844621

申请日：2010-07-27

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US20100312954A1

公开(公告)日：2010-12-09

申请号：US12844621

申请日：2010-07-27

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G06F12/02 ,  H01L23/52 ,  G06F12/00

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US07800931B2

公开(公告)日：2010-09-21

申请号：US12228590

申请日：2008-08-14

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C7/1018 ,  G11C7/08 ,  G11C11/22

摘要： In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

摘要翻译： 在能够进行稳定的脉冲串读取操作的铁电随机存取存储器件和驱动其铁电随机存取存储器件的方法中，铁电随机存取存储器件包括第一和第二存储单元部分，每个存储单元包括多个铁电存储单元 以及读取电路，其顺序地对第一和第二存储单元部分执行突发读取操作，使得第一存储单元部分的读取操作部分地与第二存储器单元部分的读取操作重叠。 当在第一存储器单元部分的读取操作期间芯片被禁止时，读取电路响应于执行第二存储器单元部分的读取操作的程度将数据写回第二存储器单元部分。

公开(公告)号：US07617351B2

公开(公告)日：2009-11-10

申请号：US11567844

申请日：2006-12-07

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G06F12/00

CPC分类号： G06F12/0638

摘要： A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in one of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

摘要翻译： 在一个芯片中具有两个不同存储区域的半导体存储器包括存储单元阵列，该存储单元阵列包括受控于至少第一和第二操作模式可访问的第一可变存储器区域和被控制为在第一和第二操作模式之一不可访问的第二可变存储区域 和第二操作模式; 以及存储器控制单元，用于存储识别第一存储区域和第二存储区域之间的区域信息，并产生用于控制对第一存储区域和第二存储区域的访问的存储器控​​制信号。 一个存储器可以替代包括一个芯片中的ROM和RAM的存储器组合。