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    STACKED FERROELECTRIC MEMORY DEVICES, METHODS OF MANUFACTURING THE SAME, FERROELECTRIC MEMORY CIRCUITS AND METHODS OF DRIVING THE SAME
    1.
    发明申请
    STACKED FERROELECTRIC MEMORY DEVICES, METHODS OF MANUFACTURING THE SAME, FERROELECTRIC MEMORY CIRCUITS AND METHODS OF DRIVING THE SAME 失效
    堆叠式电磁存储器件，其制造方法，电磁存储器电路及其驱动方法

    公开(公告)号：US20070189056A1

    公开(公告)日：2007-08-16

    申请号：US11675007

    申请日：2007-02-14

    申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

    发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

    摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

    摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

    Stacked ferroelectric memory devices, methods of manufacturing the same, ferroelectric memory circuits and methods of driving the same
    2.
    发明授权
    Stacked ferroelectric memory devices, methods of manufacturing the same, ferroelectric memory circuits and methods of driving the same 失效
    叠层铁电存储器件及其制造方法，铁电存储器电路及其驱动方法

    公开(公告)号：US07586774B2

    公开(公告)日：2009-09-08

    申请号：US11675007

    申请日：2007-02-14

    申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

    发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

    摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

    摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

    Memory device in which memory cells having complementary data are arranged
    3.
    发明授权
    Memory device in which memory cells having complementary data are arranged 失效
    具有互补数据的存储单元被布置的存储器件

    公开(公告)号：US06961271B2

    公开(公告)日：2005-11-01

    申请号：US10620022

    申请日：2003-07-14

    申请人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

    发明人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

    IPC分类号： G11C11/409 ,  G11C5/06 ,  G11C11/404 ,  G11C11/405 ,  G11C7/00

    CPC分类号： G11C11/405 ,  G11C11/404

    摘要： A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

    摘要翻译： 存储单元阵列块具有由存储单元对构成的单元存储单元，每个存储单元具有存储单元和补充存储单元。 第二单元存储单元与第一单元存储单元进行交织，第四单元存储单元与第三单元存储单元交错。 第一和第二读出放大器分别设置在阵列块的上方和下方。 第一开关将与第一单元存储单元耦合的位线与第一读出放大器连接，并将与第二单元存储单元耦合的位线与第二读出放大器相连接。 第二开关将与第三单元存储单元耦合的位线与第一读出放大器连接，并将与第四单元存储单元耦合的位线连接到第二读出放大器。 选择的单元存储单元选择性地与读出放大器连接，减少读出放大器的数量。

    Redundancy circuit of semiconductor memory device
    4.
    发明授权
    Redundancy circuit of semiconductor memory device 失效

    公开(公告)号：US06496426B2

    公开(公告)日：2002-12-17

    申请号：US09884536

    申请日：2001-06-19

    申请人： Byung-Gil Jeon ,  Ki-Nam Kim

    发明人： Byung-Gil Jeon ,  Ki-Nam Kim

    IPC分类号： G11C700

    CPC分类号： G11C29/785 ,  G11C29/808

    摘要： A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.

    Ferroelectric memory device and control method thereof
    5.
    发明授权
    Ferroelectric memory device and control method thereof 失效
    铁电存储器件及其控制方法

    公开(公告)号：US06967860B2

    公开(公告)日：2005-11-22

    申请号：US10683663

    申请日：2003-10-09

    申请人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

    发明人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

    IPC分类号： G11C11/22 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

    摘要翻译： 一种铁电随机存取存储器件，包括能够响应于地址转换产生脉冲信号的脉冲发生器电路。 芯片使能缓冲电路响应于脉冲信号的第一转换而激活芯片使能标志信号。 行选择器电路响应于地址选择并驱动其中一行。 行选择器电路还产生指示板线选择的标志信号。 响应于写入使能信号的激活，控制电路激活板控制信号，并且响应于脉冲信号的第二转换而使板控制信号无效。 根据板控制信号的激活，所选行的板线被重新激活，并且根据板控制信号的去激活而被去激活。

    Method for sensing data stored in a ferroelectric random access memory device
    6.
    发明授权
    Method for sensing data stored in a ferroelectric random access memory device 失效

    公开(公告)号：US06594174B2

    公开(公告)日：2003-07-15

    申请号：US10003528

    申请日：2001-10-30

    申请人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

    发明人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

    Node structures under capacitor in ferroelectric random access memory device and methods of forming the same
    8.
    发明申请
    Node structures under capacitor in ferroelectric random access memory device and methods of forming the same 审中-公开
    铁电随机存取存储器件中电容器下的节点结构及其形成方法

    公开(公告)号：US20080111171A1

    公开(公告)日：2008-05-15

    申请号：US11811931

    申请日：2007-06-12

    申请人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

    发明人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

    IPC分类号： H01L29/94 ,  H01L21/02

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

    摘要翻译： 在铁电随机存取存储器件中的电容器下的节点结构及其形成方法中，节点结构的顶表面设置在与节点结构周围的层间绝缘层的顶表面基本相同的水平处，并且 因此可以使电容器中的铁电体的晶体生长稳定。 为此，在半导体衬底上形成节点绝缘图案。 定义节点绝缘图案周围的节点的节点设置在节点绝缘图案之下。 节点导电图案设置在节点限定图案和节点绝缘图案之间。

    Methods for forming electronic devices including capacitor structures
    9.
    发明授权
    Methods for forming electronic devices including capacitor structures 失效
    用于形成包括电容器结构的电子器件的方法

    公开(公告)号：US06911362B2

    公开(公告)日：2005-06-28

    申请号：US10635195

    申请日：2003-08-06

    申请人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

    发明人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

    IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： Methods for forming an electronic device can include forming a capacitor structure on a portion of a substrate with the capacitor structure including a first electrode on the substrate, a capacitor dielectric on the first electrode, a second electrode on the dielectric, and a hard mask on the second electrode. More particularly, the capacitor dielectric can be between the first and second electrodes, the first electrode and the capacitor dielectric can be between the second electrode and the substrate, and the first and second electrodes and the capacitor dielectric can be between the hard mask and the substrate. An interlayer dielectric layer can be formed on the hard mask and on portions of the substrate surrounding the capacitor structure, and portions of the interlayer dielectric layer can be removed to expose the hard mask while maintaining portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor structure. The hard mask can then be removed thereby exposing portions of the second electrode while maintaining the portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor.

    摘要翻译： 用于形成电子器件的方法可以包括在衬底的一部分上形成电容器结构，其中电容器结构包括在衬底上的第一电极，第一电极上的电容器电介质，电介质上的第二电极， 第二电极。 更具体地，电容器电介质可以在第一和第二电极之间，第一电极和电容器电介质可以在第二电极和衬底之间，并且第一和第二电极和电容器电介质可以在硬掩模和第二电极之间 基质。 可以在硬掩模和围绕电容器结构的基板的部分上形成层间电介质层，并且可以去除层间介电层的部分以暴露硬掩模，同时将层间电介质层的部分保持在基板的部分上 围绕电容器结构。 然后可以去除硬掩模，从而暴露第二电极的部分，同时保持层间电介质层的部分在包围电容器的基板的部分上。