公开(公告)号：US07586774B2

公开(公告)日：2009-09-08

申请号：US11675007

申请日：2007-02-14

申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

公开(公告)号：US20070189056A1

公开(公告)日：2007-08-16

申请号：US11675007

申请日：2007-02-14

申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

公开(公告)号：US20070158731A1

公开(公告)日：2007-07-12

申请号：US11620225

申请日：2007-01-05

申请人： Byoung-Jae Bae ,  Byung-Gil Jeon ,  Heung-Jin Joo ,  Dong-Chul Yoo ,  Sang-Don Nam

发明人： Byoung-Jae Bae ,  Byung-Gil Jeon ,  Heung-Jin Joo ,  Dong-Chul Yoo ,  Sang-Don Nam

IPC分类号： H01L29/76

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

摘要： A memory device includes one or more layers of parallel strings of ferroelectric gate transistors on a substrate, each layer of parallel strings including a plurality of parallel line-shaped active regions and a plurality of word lines extending in parallel transversely across the active regions and disposed on ferroelectric patterns on the active regions. A string select gate line may extend transversely across the active regions in parallel with the word lines. A ground select gate line may extend transversely across the active regions in parallel with the word lines.

摘要翻译： 存储器件包括在衬底上的一层或多层平行的铁电栅极晶体管层，每层平行的串包括多个平行的线状有源区和跨越有源区并行延伸的多条字线， 关于活跃区域的铁电模式。 串选择栅极线可以横跨有源区域与字线平行地延伸。 接地选择栅极线可以与字线平行地跨越有源区横向延伸。

公开(公告)号：US07106617B2

公开(公告)日：2006-09-12

申请号：US11029616

申请日：2005-01-05

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

公开(公告)号：US06496426B2

公开(公告)日：2002-12-17

申请号：US09884536

申请日：2001-06-19

申请人： Byung-Gil Jeon ,  Ki-Nam Kim

发明人： Byung-Gil Jeon ,  Ki-Nam Kim

IPC分类号： G11C700

CPC分类号： G11C29/785 ,  G11C29/808

摘要： A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.

公开(公告)号：US06961271B2

公开(公告)日：2005-11-01

申请号：US10620022

申请日：2003-07-14

申请人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

发明人： Byung-Gil Jeon ,  Ki-Nam Kim ,  Mun-Kyu Choi

IPC分类号： G11C11/409 ,  G11C5/06 ,  G11C11/404 ,  G11C11/405 ,  G11C7/00

CPC分类号： G11C11/405 ,  G11C11/404

摘要： A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

摘要翻译： 存储单元阵列块具有由存储单元对构成的单元存储单元，每个存储单元具有存储单元和补充存储单元。 第二单元存储单元与第一单元存储单元进行交织，第四单元存储单元与第三单元存储单元交错。 第一和第二读出放大器分别设置在阵列块的上方和下方。 第一开关将与第一单元存储单元耦合的位线与第一读出放大器连接，并将与第二单元存储单元耦合的位线与第二读出放大器相连接。 第二开关将与第三单元存储单元耦合的位线与第一读出放大器连接，并将与第四单元存储单元耦合的位线连接到第二读出放大器。 选择的单元存储单元选择性地与读出放大器连接，减少读出放大器的数量。

公开(公告)号：US06847537B2

公开(公告)日：2005-01-25

申请号：US10358550

申请日：2003-02-05

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

摘要翻译： 铁电存储器件包括铁电存储器单元。 铁电存储单元具有至少一个位线和板线。 控制电路在写入操作期间与写入线的激活基本同时地驱动具有写入数据的至少一个位线。 存储器件还可以包括耦合到铁电存储单元的读出放大器，并且控制电路还可以被配置为在读取操作期间与读出放大器的激活基本同时地去激活平板线。

公开(公告)号：US07313011B2

公开(公告)日：2007-12-25

申请号：US11491872

申请日：2006-07-24

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

摘要翻译： 铁电存储器件包括铁电存储器单元。 铁电存储单元具有至少一个位线和板线。 控制电路在写入操作期间与写入线的激活基本同时地驱动具有写入数据的至少一个位线。 存储器件还可以包括耦合到铁电存储单元的读出放大器，并且控制电路还可以被配置为在读取操作期间与读出放大器的激活基本同时地去激活平板线。

公开(公告)号：US20060256607A1

公开(公告)日：2006-11-16

申请号：US11491872

申请日：2006-07-24

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

摘要翻译： 铁电存储器件包括铁电存储器单元。 铁电存储单元具有至少一个位线和板线。 控制电路在写入操作期间与写入线的激活基本同时地驱动具有写入数据的至少一个位线。 存储器件还可以包括耦合到铁电存储单元的读出放大器，并且控制电路还可以被配置为在读取操作期间与读出放大器的激活基本同时地去激活平板线。

公开(公告)号：US06967860B2

公开(公告)日：2005-11-22

申请号：US10683663

申请日：2003-10-09

申请人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

发明人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

IPC分类号： G11C11/22 ,  G11C7/22

CPC分类号： G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

摘要翻译： 一种铁电随机存取存储器件，包括能够响应于地址转换产生脉冲信号的脉冲发生器电路。 芯片使能缓冲电路响应于脉冲信号的第一转换而激活芯片使能标志信号。 行选择器电路响应于地址选择并驱动其中一行。 行选择器电路还产生指示板线选择的标志信号。 响应于写入使能信号的激活，控制电路激活板控制信号，并且响应于脉冲信号的第二转换而使板控制信号无效。 根据板控制信号的激活，所选行的板线被重新激活，并且根据板控制信号的去激活而被去激活。