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公开(公告)号：US20240333234A1
公开(公告)日：2024-10-03
申请号：US18743889
申请日：2024-06-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kiichiro TAKENAKA
CPC classification number: H03F1/56 , H03F1/0288 , H03F3/211 , H03F2200/387
Abstract: A power amplifier circuit includes: a first power splitter that splits an input signal into a first input signal and a second input signal; a Doherty amplifier circuit that includes a carrier amplifier and a peak amplifier and that amplifies the first input signal and outputs an output signal to an output terminal; and a control amplifier that amplifies the second input signal and outputs, to the Doherty amplifier circuit, a control signal for controlling load impedance of the Doherty amplifier circuit.
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公开(公告)号：US20220256477A1
公开(公告)日：2022-08-11
申请号：US17652136
申请日：2022-02-23
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi TANAKA , Kiichiro TAKENAKA , Takayuki TSUTSUI , Taizo YAMAWAKI , Shun IMAI
Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
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公开(公告)号：US20200374811A1
公开(公告)日：2020-11-26
申请号：US16989993
申请日：2020-08-11
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi TANAKA , Kiichiro TAKENAKA , Takayuki TSUTSUI , Taizo YAMAWAKI , Shun IMAI
Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
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公开(公告)号：US20200350867A1
公开(公告)日：2020-11-05
申请号：US16931965
申请日：2020-07-17
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kiichiro TAKENAKA
Abstract: A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.
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公开(公告)号：US20190199298A1
公开(公告)日：2019-06-27
申请号：US16217506
申请日：2018-12-12
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kiichiro TAKENAKA , Masahiro ITO , Tsuyoshi SATO , Kozo SATO , Hidetoshi MATSUMOTO
Abstract: A matching network is a matching network of a power amplifier circuit that outputs a signal obtained by a differential amplifier amplifying power of a high-frequency signal. The matching network includes an input-side winding connected between differential outputs of the differential amplifier; an output-side winding that is coupled to the input-side winding via an electromagnetic field and whose one end is connected to a reference potential; a first LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the input-side winding; and a second LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the output-side winding.
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Patent Agency Ranking
公开(公告)号：US20190081599A1
公开(公告)日：2019-03-14
申请号：US16188582
申请日：2018-11-13
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kiichiro TAKENAKA
CPC classification number: H03F3/211 , H01F27/00 , H03F1/0288 , H03F3/4508 , H03F3/45179 , H03F3/45475 , H03F2200/451 , H03F2200/537 , H03F2200/541 , H03K2005/00286
Abstract: A power amplifier circuit includes: a first differential amplifier that amplifies a first signal split from the input signal and outputs a second signal; a second differential amplifier that amplifies a third signal split from the input signal and outputs a fourth signal; a first transformer including a first input-side winding to which the second signal is input and a first output-side winding; a second transformer including a second input-side winding to which the fourth signal is input and a second output-side winding; a first phase conversion element that is connected in parallel with the first output-side winding and outputs a fifth signal; and a second phase conversion element that is connected in parallel with the second output-side winding and outputs a sixth signal. The first and second output-side windings are connected in series and output a signal obtained by adding voltages of the fifth and sixth signals together.
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公开(公告)号：US20240322758A1
公开(公告)日：2024-09-26
申请号：US18668341
申请日：2024-05-20
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yuuma NOGUCHI , Kiichiro TAKENAKA , Tomohide ARAMATA , Takeshi KOGURE , Takaya WADA
CPC classification number: H03F1/0233 , H03F3/245 , H03F2200/105 , H03F2200/451
Abstract: A power amplifier circuit includes a power amplifier configured to amplify radio-frequency signal, a supply voltage terminal coupled to the power amplifier, and a bypass capacitor coupled between ground and a supply voltage path connecting the supply voltage terminal to the power amplifier. A supply voltage (VDET) is configured to be supplied to the power amplifier through the supply voltage terminal, and the supply voltage (VDET) is configured to vary across multiple discrete voltage levels within a single frame of radio-frequency signals. The first bypass capacitor has an electrostatic capacity equal to or higher than a specific value that is determined to cause the power amplifier circuit with the first supply voltage to have a higher efficiency than a threshold efficiency. In some exemplary embodiments, the bypass capacitor has an electrostatic capacity equal to or higher than 1.4 nanofarads.
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公开(公告)号：US20220294395A1
公开(公告)日：2022-09-15
申请号：US17805277
申请日：2022-06-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi TANAKA , Kiichiro TAKENAKA , Satoshi ARAYASHIKI , Satoshi SAKURAI
Abstract: A Doherty amplifier including a main amplifier and a peak amplifier is mounted on a package substrate. A low noise amplifier is further mounted on the package substrate. A transmit/receive switch switches in terms of time between a transmission connection state in which an output signal of the Doherty amplifier is supplied to an antenna and a reception connection state in which a signal received by the antenna is inputted to the low noise amplifier.
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公开(公告)号：US20210194444A1
公开(公告)日：2021-06-24
申请号：US17123230
申请日：2020-12-16
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masao KONDO , Kiichiro TAKENAKA , Satoshi TANAKA , Takayuki TSUTSUI
Abstract: A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.
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公开(公告)号：US20200212855A1
公开(公告)日：2020-07-02
申请号：US16720308
申请日：2019-12-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yuuma NOGUCHI , Hidetoshi MATSUMOTO , Kiichiro TAKENAKA , Satoshi TANAKA
Abstract: A power supply circuit supplies a variable voltage to a power amplifier that amplifies a radio-frequency signal, and includes a transistor and a current detecting resistor. The transistor includes a collector or drain that is supplied with a fixed voltage from a fixed voltage source, a base or gate that receives an envelope signal tracking an envelope of the radio-frequency signal, and an emitter or source that outputs the variable voltage that is based on the envelope signal. The current detecting resistor is electrically connected between the fixed voltage source and the collector or drain of the transistor.
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