-
公开(公告)号：US20220029004A1
公开(公告)日：2022-01-27
申请号：US17495588
申请日：2021-10-06
发明人： Isao OBU , Yasunari UMEMOTO , Masahiro SHIBATA , Shigeki KOYA , Masao KONDO , Takayuki TSUTSUI
IPC分类号： H01L29/737 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L21/306 , H01L21/02 , H01L21/285 , H01L21/311 , H01L21/308 , H01L29/66 , H03F3/213 , H03F3/195 , H01L29/205 , H03F3/21 , H03F1/56 , H03F3/24 , H01L23/00
摘要： A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
-
公开(公告)号：US20200296839A1
公开(公告)日：2020-09-17
申请号：US16814902
申请日：2020-03-10
发明人： Masao KONDO , Shigeki KOYA , Kenji SASAKI
IPC分类号： H05K3/24 , H01L21/48 , H01L23/538
摘要： A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
-
公开(公告)号：US20190109066A1
公开(公告)日：2019-04-11
申请号：US16153310
申请日：2018-10-05
发明人： Masao KONDO , Masahiro SHIBATA
IPC分类号： H01L23/367 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/737 , H01L29/417 , H01L23/498 , H01L23/00 , H03F3/21 , H03F1/30
摘要： A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.
-
公开(公告)号：US20240096792A1
公开(公告)日：2024-03-21
申请号：US18522110
申请日：2023-11-28
发明人： Satoshi GOTO , Masao KONDO , Shigeki KOYA , Takayuki TSUTSUI
IPC分类号： H01L23/528 , H01L23/00 , H01L23/64 , H01L25/065
CPC分类号： H01L23/528 , H01L23/64 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L24/16 , H01L2224/16225 , H01L2224/32227 , H01L2224/32238 , H01L2224/48229 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2924/19011
摘要： A semiconductor module comprises a first member including a semiconductor substrate made of a compound semiconductor and a first electronic circuit on the semiconductor substrate is mounted on a mounting surface of a module substrate, and a second member including a semiconductor layer formed of a single semiconductor thinner than the semiconductor substrate of the first member and a second electronic circuit on the semiconductor layer is bonded to an upper surface of the first member. First and second pads are respectively connected to the first electronic circuit on the first member and the second electronic circuit on the second member. A first wire connects the first pad and a substrate side pad. A second wire connects the second pad and a substrate side pad. An inter-member connection wire made of a conductor film on the first and second members connects the first and second electronic circuits.
-
公开(公告)号：US20200251579A1
公开(公告)日：2020-08-06
申请号：US16854262
申请日：2020-04-21
发明人： Isao OBU , Yasunari UMEMOTO , Masahiro SHIBATA , Shigeki KOYA , Masao KONDO , Takayuki TSUTSUI
IPC分类号： H01L29/737 , H01L29/205 , H03F3/195 , H03F3/213 , H01L29/66 , H01L21/308 , H01L21/311 , H01L21/285 , H01L21/02 , H01L21/306 , H01L29/423 , H01L29/417 , H01L29/08 , H01L29/10 , H01L23/00 , H03F3/24 , H03F1/56 , H03F3/21
摘要： A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
-
公开(公告)号：US20200186094A1
公开(公告)日：2020-06-11
申请号：US16789827
申请日：2020-02-13
发明人： Masao KONDO , Hidetoshi MATSUMOTO
摘要： A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.
-
公开(公告)号：US20170359038A1
公开(公告)日：2017-12-14
申请号：US15600993
申请日：2017-05-22
发明人： Satoshi TANAKA , Kazuo WATANABE , Takayuki TSUTSUI , Masao KONDO , Satoshi ARAYASHIKI , Fumio HARIMA , Masatoshi HASE
IPC分类号： H03F3/24 , H04L5/14 , H03F3/21 , H03F3/195 , H04L5/00 , H03F1/56 , H03F1/02 , H03F3/00 , H04W88/00
CPC分类号： H03F3/245 , H03F1/0205 , H03F1/0272 , H03F1/0277 , H03F1/22 , H03F1/565 , H03F3/005 , H03F3/195 , H03F3/21 , H03F2200/222 , H03F2200/318 , H03F2200/387 , H03F2200/408 , H03F2200/451 , H03F2200/555 , H04L5/0007 , H04L5/14 , H04W88/00
摘要： A power amplifier circuit includes first and second transistors and a first voltage output circuit. A radio frequency signal is input into a base of the first transistor. The first voltage output circuit outputs a first voltage in accordance with a power supply voltage. The first voltage is supplied to a base or a gate of the second transistor. An emitter or a source of the second transistor is connected to a collector of the first transistor. A first amplified signal generated by amplifying the radio frequency signal is output from a collector or a drain of the second transistor.
-
公开(公告)号：US20240096824A1
公开(公告)日：2024-03-21
申请号：US18523320
申请日：2023-11-29
IPC分类号： H01L23/66 , H01L25/065 , H03F1/56 , H03F3/195 , H03F3/24
CPC分类号： H01L23/66 , H01L25/0657 , H03F1/565 , H03F3/195 , H03F3/245 , H01L2223/6611 , H01L2223/6655 , H01L2225/06503
摘要： A stacked semiconductor device capable of increasing heat dissipation comprises a first member and a second member. The first member includes a semiconductor substrate and a first electronic circuit. The first electronic circuit includes a semiconductor element provided on one surface of the semiconductor substrate. A second member is attached to a first surface, which is one surface of the first member. The second member includes a second electronic circuit including another semiconductor element. The second member is provided with a first opening that penetrates the second member in a thickness direction. A first conductor projection is coupled to the first electronic circuit. The first conductor projection protrudes from the first surface of the first member through the first opening of the second member to the outside of the first opening.
-
公开(公告)号：US20210327775A1
公开(公告)日：2021-10-21
申请号：US17224784
申请日：2021-04-07
发明人： Shigeki KOYA , Yoshimitsu TAKENOUCHI , Kenji SASAKI , Masao KONDO
摘要： An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.
-
公开(公告)号：US20210194444A1
公开(公告)日：2021-06-24
申请号：US17123230
申请日：2020-12-16
摘要： A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.017 秒)
