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公开(公告)号：US20210118614A1
公开(公告)日：2021-04-22
申请号：US17137498
申请日：2020-12-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA , Shogo KANBE , Kosuke NAKANO , Hideki OTSUKA
Abstract: A chip electronic component includes spacers that each have a predetermined thickness direction dimension on a mounting surface in a direction perpendicular to the mounting surface. The spacers each contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal.
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公开(公告)号：US20180158608A1
公开(公告)日：2018-06-07
申请号：US15828472
申请日：2017-12-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA , Takashi FUKUMA
Abstract: An electronic component includes a multilayer capacitor and an interposer including a substrate main body with an electric insulation property, the multilayer capacitor being mounted on one main surface side of the substrate main body. The multilayer capacitor includes a multilayer body, a first outer electrode, and a second outer electrode. The multilayer body includes an effective region and a non-effective region surrounding the effective region. A width of the effective region is larger than a width of the substrate main body, when a width of the multilayer body is represented by W11, a thickness of the multilayer body is represented by T11, and a thickness of the substrate main body is represented by T21, a value of W11/(T11+T21) is not less than about 0.90 and not more than about 1.10.
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13.发明申请MONOLITHIC CERAMIC CAPACITOR, MONOLITHIC CERAMIC CAPACITOR ARRAY, AND MONOLITHIC CERAMIC CAPACITOR MOUNTING STRUCTURE 有权单晶陶瓷电容器，单晶陶瓷电容阵列和单晶陶瓷电容器安装结构公开(公告)号：US20150228409A1
公开(公告)日：2015-08-13
申请号：US14616787
申请日：2015-02-09
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA , Tadateru YAMADA
CPC classification number: H01G4/30 , H01G4/012 , H01G4/12 , H01G4/129 , H01G4/248 , H05K1/183 , H05K2201/10015
Abstract: A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B.
Abstract translation: 单片陶瓷电容器包括陶瓷体中的多个第一和第二内部电极。 层叠第一和第二内部电极的方向是层叠方向，与陶瓷体的层叠方向垂直或大致垂直的方向为长度方向，垂直于或大致垂直于层叠方向的方向，第一 方向是宽度方向。 陶瓷体包括有效部分，第一外层部分，第二外层部分，第一侧部分和第二侧部分。 第一侧部分和第二侧面部分在宽度方向上的尺寸为A，层叠方向上有效部分的尺寸为B时，A / B比约为0.04以下。
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公开(公告)号：US20230162919A1
公开(公告)日：2023-05-25
申请号：US18101132
申请日：2023-01-25
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Seiji HIDAKA , Yukihiro FUJITA
Abstract: A multi-terminal multilayer capacitor includes first vias and second vias extending in first and second internal electrodes in a stacking direction, a first slit extending between the first via and a first insulating portion that insulates the second via and the first internal electrode from each other, and a second slit extending between the second via and a second insulating portion that insulates the first via and the second internal electrode from each other. The first via electrically connects regions of the first internal electrode split by the first slit, and the second via electrically connects regions of the second internal electrode divided by the second slit.
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15.发明公开公开(公告)号：US20230145085A1
公开(公告)日：2023-05-11
申请号：US18093832
申请日：2023-01-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA
Abstract: A multilayer capacitor includes a capacitor body including dielectric layers, first and second internal electrodes, and first and second main surfaces, first and second external electrodes on at least one of the first and second main surfaces, first via conductors to electrically connect the first external electrode and the first internal electrodes, and second via conductors to electrically connect the second external electrode and the second internal electrodes, a direction in which the dielectric layer, the first internal electrode, and the second internal electrode are laminated is a height direction of the capacitor body, and a height of the capacitor body is about 100%, and a height of the first and second external electrodes is equal to or larger than about 50% with respect to the height of the capacitor body.
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Patent Agency Ranking
公开(公告)号：US20190287719A1
公开(公告)日：2019-09-19
申请号：US16427551
申请日：2019-05-31
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA , Shogo KANBE , Kosuke NAKANO , Hideki OTSUKA
Abstract: A chip electronic component includes spacers that each have a predetermined thickness direction dimension on a mounting surface in a direction perpendicular to the mounting surface. The spacers each contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal.
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公开(公告)号：US20240387113A1
公开(公告)日：2024-11-21
申请号：US18786661
申请日：2024-07-29
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kengo KAKOMURA , Yukihiro FUJITA , Seiji HIDAKA
Abstract: A multilayer ceramic capacitor includes a capacitor body including dielectric layers, first and second inner electrodes, first and second via conductors, and first and second outer electrodes. In a reference layout in which m×n (m and n are each a natural number of 4 or more) virtual lattice points are set in a view of the capacitor body seen in a lamination direction, and in which the first and second via conductors are arranged at all the virtual lattice points, the first and second via conductors are not arranged at least in a portion of (m-2)×(n-2) of the virtual lattice points located inside outermost peripheral virtual lattice points.
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公开(公告)号：US20230274881A1
公开(公告)日：2023-08-31
申请号：US18195426
申请日：2023-05-10
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA , Shogo KANBE , Kosuke NAKANO , Hideki OTSUKA
Abstract: A chip electronic component includes spacers that each have a predetermined thickness direction dimension on a mounting surface in a direction perpendicular to the mounting surface. The spacers each contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal.
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公开(公告)号：US20180160541A1
公开(公告)日：2018-06-07
申请号：US15830233
申请日：2017-12-04
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA
Abstract: A multilayer capacitor built-in substrate includes a core substrate, a multilayer capacitor mounted on one principal surface of the core substrate, and a burying layer provided on the one principal surface of the core substrate to bury the multilayer capacitor. The multilayer capacitor includes a laminated body in which dielectric layers and internal electrode layers are laminated, and first and second external electrodes. The laminated body includes an effective region in which internal electrode layers respectively connected to the first external electrode and the second external electrode are laminated with a dielectric layer located therebetween, and a non-effective region surrounding the effective region. The core substrate includes, on the one principal surface, a first land electrode electrically connected to the first external electrode and a second land electrode electrically connected to the second external electrode.
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20.发明申请MONOLITHIC CERAMIC CAPACITOR, MONOLITHIC CERAMIC CAPACITOR ARRAY, AND MONOLITHIC CERAMIC CAPACITOR MOUNTING STRUCTURE 有权单晶陶瓷电容器，单晶陶瓷电容阵列和单晶陶瓷电容器安装结构公开(公告)号：US20170062135A1
公开(公告)日：2017-03-02
申请号：US15351517
申请日：2016-11-15
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yukihiro FUJITA , Tadateru YAMADA
CPC classification number: H01G4/30 , H01G4/012 , H01G4/12 , H01G4/129 , H01G4/248 , H05K1/183 , H05K2201/10015
Abstract: A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B.
Abstract translation: 单片陶瓷电容器包括陶瓷体中的多个第一和第二内部电极。 层叠第一和第二内部电极的方向是层叠方向，与陶瓷体的层叠方向垂直或大致垂直的方向为长度方向，垂直于或大致垂直于层叠方向的方向，第一 方向是宽度方向。 陶瓷体包括有效部分，第一外层部分，第二外层部分，第一侧部分和第二侧部分。 第一侧部分和第二侧面部分在宽度方向上的尺寸为A，层叠方向上有效部分的尺寸为B时，A / B比约为0.04以下。
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