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公开(公告)号：US06763508B2
公开(公告)日：2004-07-13
申请号：US10122402
申请日：2002-04-12
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit configured to register a list expressing an optimum wire terminating process for each via shape of said basic via shape list registered in said library information storage unit; and a central processing control unit configured to refer to the lists respectively registered in said library information storage unit and said technology database storage unit, select an optimum line processing, and execute a line design.
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公开(公告)号：US07013444B2
公开(公告)日：2006-03-14
申请号：US10824857
申请日：2004-04-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit configured to register a list expressing an optimum wire terminating process for each via shape of said basic via shape list registered in said library information storage unit; and a central processing control unit configured to refer to the lists respectively registered in said library information storage unit and said technology database storage unit, select an optimum line processing, and execute a line design.
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公开(公告)号：US07124389B2
公开(公告)日：2006-10-17
申请号：US10848102
申请日：2004-05-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.
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公开(公告)号：US06779167B2
公开(公告)日：2004-08-17
申请号：US10133953
申请日：2002-04-26
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.
摘要翻译： 提供了一种自动布线图案布局方法。 利用该方法，产生具有宽度W并沿第一方向延伸的第一布线图案，并且以宽度W产生第二布线图案并且沿垂直于第一布线图案的方向延伸，使得其端部结束 在第一布线图案的端部。 此外，通过将第一或第二布线图案中的任一个的端部以直角弯曲而产生重叠区域以产生L形延伸部并且覆盖第一和第二布线图案，并且形成矩形VIA图案 在重叠区域产生。
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公开(公告)号：US06792593B2
公开(公告)日：2004-09-14
申请号：US10133683
申请日：2002-04-25
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： In a pattern correction method, design layout data of a pattern designed by an automated layout unit is entered. An environmental profile is determined based on whether or not another graphics pattern exists at the surroundings of each correction target cell included in the entered design layout data. A target cell name is replaced with a prescribed cell name of correction pattern corresponding to the determined environmental profile by referencing a cell replacement table. An OPC correction pattern corresponding to the replaced cell name is imported from a cell library.
摘要翻译： 在图案校正方法中，输入由自动布局单元设计的图案的设计布局数据。 基于在输入的设计布局数据中包括的每个校正目标单元的周围是否存在另一图形模式来确定环境简档。 通过参照小区替换表，将目标小区名称替换为与确定的环境简档对应的校正模式的规定小区名称。 从更换的单元格名称对应的OPC校正模式从单元库导入。
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16.发明授权Semiconductor integrated circuit and supply method for supplying multiple supply voltages in a semiconductor integrated circuit 失效用于在半导体集成电路中提供多个电源电压的半导体集成电路和供电方法
公开(公告)号：US06097043A
公开(公告)日：2000-08-01
申请号：US996998
申请日：1997-12-23
申请人： Mutsunori Igarashi , Hiroshi Tanaka , Kimiyoshi Usami , Takashi Ishikawa , Masahiro Kanazawa , Chiharu Mizuno
发明人： Mutsunori Igarashi , Hiroshi Tanaka , Kimiyoshi Usami , Takashi Ishikawa , Masahiro Kanazawa , Chiharu Mizuno
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L23/528 , H01L27/04 , H01L23/50
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).
摘要翻译： 一种半导体集成电路，提供多个电源电压的供给方法，以及用于存储提供多个电压的供给方法的程序的记录介质，由此提供提供多个电源电压的第一单元（步骤S1） ，将提取的单元分成组（步骤S2），根据组的数量添加并排列用于电压供给的单元（步骤S3），并且用于供电的单元连接到用于提供多个单元的第一单元 的电压通过网络供电（步骤S4）。
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17.发明申请Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit 失效计算机实现设计系统，计算机实现设计方法，光罩组和集成电路公开(公告)号：US20070011638A1
公开(公告)日：2007-01-11
申请号：US11522049
申请日：2006-09-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/36 , H01L27/11803
摘要： A reticle set includes a first reticle including a first wiring pattern having a first termination pattern; a second reticle including a plurality of via patterns; and a third reticle including a second wiring pattern having a second termination pattern and a second line pattern connected to an end of the second termination pattern.
摘要翻译： 标线组包括：第一掩模版，其包括具有第一端接图案的第一布线图案; 包括多个通孔图案的第二掩模版; 以及第三掩模版，其包括具有第二端接图案的第二布线图案和连接到所述第二端接图案的端部的第二线图案。
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18.发明授权Method, apparatus and program for designing a semiconductor integrated circuit by adjusting loading of paths 失效通过调整路径负载来设计半导体集成电路的方法，装置和程序公开(公告)号：US06904572B2
公开(公告)日：2005-06-07
申请号：US10378731
申请日：2003-03-03
申请人： Mutsunori Igarashi
发明人： Mutsunori Igarashi
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/505
摘要： A computer-implemented method for designing a semiconductor integrated circuit, which optimizes the propagation delay of a path from a signal input terminal (source) to a signal output terminal (sink) on the same net, includes: calculating the ratio of the total sum of a gate input load capacitance to the wiring capacitance of the path from the source to the sink as a process variation sensitivity relating to the capacitance component of the path to be designed from the source to the sink, based on a circuit design information of a gate level of the semiconductor integrated circuit to be designed; and optimizing the process variation sensitivity relating to the capacitance component of each path in order that the process variation sensitivities relating to the capacitance components of all the paths are smaller than a reference value.
摘要翻译： 一种用于设计半导体集成电路的计算机实现的方法，其优化从同一网络上的信号输入端（源）到信号输出端（汇）的路径的传播延迟，包括：计算总和 基于从源到宿的电路设计信息，从源到宿的路径的布线电容的栅极输入负载电容作为与从源到宿设计的路径的电容分量有关的过程变化灵敏度 要设计的半导体集成电路的栅极电平; 并且优化与每个路径的电容分量相关的过程变化灵敏度，以使与所有路径的电容分量相关的过程变化灵敏度小于参考值。
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公开(公告)号：US5986961A
公开(公告)日：1999-11-16
申请号：US955530
申请日：1997-10-22
申请人： Mutsunori Igarashi
发明人： Mutsunori Igarashi
摘要： A semiconductor integrated circuit of a low power consumption type has modules (1) to which various supply voltages are provided. In each module (1), cells (3) are grouped into cell rows or cell columns. Only one of a wire (7) of a high supply voltage and a wire (5) of a low supply voltage is formed on each cell row or cell column in the module (1). Various supply voltages are provided into the target cell (3) through the electrical wires (5, 7).
摘要翻译： 低功耗型的半导体集成电路具有提供各种电源电压的模块（1）。 在每个模块（1）中，单元格（3）被分组成单元行或单元列。 在模块（1）中的每个单元行或单元列上仅形成高电源线（7）中的一个和低电源电压的导线（5）中的一个。 通过电线（5,7）向目标电池（3）提供各种电源电压。
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20.发明授权
公开(公告)号：US5397749A
公开(公告)日：1995-03-14
申请号：US910525
申请日：1992-07-08
申请人： Mutsunori Igarashi
发明人： Mutsunori Igarashi
IPC分类号： H01L21/82 , G06F17/50 , H01L27/02 , H01L27/118 , H01L21/00
CPC分类号： H01L27/0207
摘要： A method for arranging a group of logical cells through which a signal is transmitted within an allowable delay time, consisting of the steps of determining signal lines interconnecting the logical cells of the equipotential net, defining a critical path consisting of the signal lines of all the equipotential nets, classifying the logical cells positioned between the equipotential nets as path core cells and classifying the other logical cells as path branch cells, positioning the path core cells to shorten the length of a main signal route passing through the path core cells, positioning the path branch cells to shorten the distance between the main signal route and the path branch cell for each equipotential net, and decreasing the delay time of the critical path formed by the replaced path core cells and the replaced path branch cells within the allowable delay time.
摘要翻译： 一种用于布置在允许的延迟时间内通过其发送信号的一组逻辑单元的方法，包括确定连接等电位网络的逻辑单元的信号线的步骤，所述信号线定义了由所有这些信号线的信号线组成的关键路径 等位网络，将位于等电位网之间的逻辑单元分类为路径核心小区，并将其他逻辑单元分类为路径分支小区，定位路径核心单元以缩短通过路径核心小区的主信号路由的长度， 路径分支小区，以缩短每个等势网的主信号路径和路径分支小区之间的距离，并且将由替换的路径核心小区和替换的路径分支小区形成的关键路径的延迟时间减少到可允许的延迟时间内。
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