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公开(公告)号：US20230363293A1
公开(公告)日：2023-11-09
申请号：US18101700
申请日：2023-01-26
Applicant: NEC Corporation
Inventor： Akira Miyata , Tsuyoshi Yamamoto
CPC classification number: H10N60/12 , G06N10/40 , H10N60/805
Abstract: A superconducting quantum circuit apparatus includes a resonator including a SQUID including at least two Josephson junctions in a loop, a magnetic field application part that includes a conductor portion, a current passing therethrough generating a magnetic flux penetrating through the SQUID, the current supplied from a current control part, and a parallel LC circuit including an inductor and a capacitor each made of a superconducting material, the inductor and the capacitor having respective one ends connected in common to the magnetic field application part and respective other ends connected in common to a current path from the current control part.
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公开(公告)号：US11658613B2
公开(公告)日：2023-05-23
申请号：US17573841
申请日：2022-01-12
Applicant: NEC Corporation
Inventor： Yoshihito Hashimoto , Tsuyoshi Yamamoto , Tomohiro Yamaji
CPC classification number: H03B15/003 , H01L39/223
Abstract: An oscillator in which crosstalk can be reduced is provided. An oscillator includes a SQUID, a transmission line connected to the SQUID, a ground plane, and a first connection circuit disposed in a vicinity of a node of an electric field of a standing wave that is generated when the oscillator is oscillating, the first connection circuit connecting parts of the ground plane located on both sides of the transmission line to each other.
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公开(公告)号：US11915100B2
公开(公告)日：2024-02-27
申请号：US17115971
申请日：2020-12-09
Applicant: NEC CORPORATION
Inventor： Tomohiro Yamaji , Tsuyoshi Yamamoto
CPC classification number: G06N10/00 , G06N10/40 , H03B15/003 , H10N60/805 , H10N60/82
Abstract: A resonator, an oscillator, and a quantum computer capable of preventing oscillation conditions for generating a parametric oscillation from becoming complicated are provided. A resonator includes at least one loop circuit in which a first superconducting line, a first Josephson junction, a second superconducting line, and a second Josephson junction are connected in a ring shape, in which critical current values of the first and second Josephson junctions are different from each other.
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公开(公告)号：US20220377879A1
公开(公告)日：2022-11-24
申请号：US17746172
申请日：2022-05-17
Applicant: NEC Corporation
Inventor： Yoshihito HASHIMOTO , Tsuyoshi Yamamoto , Kohei Matsuura
Abstract: A sample holder includes a base comprising a support structure and a printed circuit board (PCB) in contact with the base. The PCB includes: a dielectric; a front-surface ground (GND) formed on a front surface of the dielectric; a back-surface GND formed on a back surface of the dielectric; a through hole penetrating from the front-surface GND to the back-surface GND, the through hole in which a chip is disposed, and a conductor that electrically connects the front-surface GND and the back-surface GND on an end face of the through hole. At least a part of the base below the through hole has a cavity. The support structure that supports a surface of the chip and is electrically connected to the base. The support structure is disposed in the cavity.
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公开(公告)号：US10819281B2
公开(公告)日：2020-10-27
申请号：US16519280
申请日：2019-07-23
Applicant: KABUSHIKI KAISHA TOSHIBA , NEC CORPORATION
Inventor： Hayato Goto , Tsuyoshi Yamamoto
Abstract: According to one embodiment, an electronic circuit includes a first conductive component, a second conductive component, a first current path, and a second current path. The second conductive component is capacitively coupled to the first conductive component. The first current path of a superconductor includes a first portion and a second portion. The first portion is connected to the first conductive component. The second portion is connected to the second conductive component. The first current path includes N first Josephson junctions connected in series and provided between the first and second portions. The second current path of a superconductor includes a third portion and a fourth portion. The third portion is connected to the first conductive component. The fourth portion is connected to the second conductive component. The second current path includes a second Josephson junction connected in series and provided between the third and fourth portions.
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Patent Agency Ranking
公开(公告)号：US12232248B2
公开(公告)日：2025-02-18
申请号：US17746212
申请日：2022-05-17
Applicant: NEC Corporation
Inventor： Yoshihito Hashimoto , Tsuyoshi Yamamoto , Kohei Matsuura
Abstract: A sample holder includes a base comprising a support structure and a printed circuit board (PCB) in contact with the base. The PCB has a through hole. The PCB has a cavity in at least a part of the base below the through hole. The support structure that supports a surface of a chip and is electrically connected to the base. The support structure is disposed in the cavity. At least a part of the section supporting the chip in the support structure is not parallel to the back surface of the chip.
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公开(公告)号：US11956889B2
公开(公告)日：2024-04-09
申请号：US17746172
申请日：2022-05-17
Applicant: NEC Corporation
Inventor： Yoshihito Hashimoto , Tsuyoshi Yamamoto , Kohei Matsuura
CPC classification number: H05K1/0237 , H05K1/115 , H05K1/183
Abstract: A sample holder includes a base comprising a support structure and a printed circuit board (PCB) in contact with the base. The PCB includes: a dielectric; a front-surface ground (GND) formed on a front surface of the dielectric; a back-surface GND formed on a back surface of the dielectric; a through hole penetrating from the front-surface GND to the back-surface GND, the through hole in which a chip is disposed, and a conductor that electrically connects the front-surface GND and the back-surface GND on an end face of the through hole. At least a part of the base below the through hole has a cavity. The support structure that supports a surface of the chip and is electrically connected to the base. The support structure is disposed in the cavity.
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公开(公告)号：US20230422636A1
公开(公告)日：2023-12-28
申请号：US18039207
申请日：2020-12-04
Applicant: NEC Corporation
Inventor： Tetsuro Sato , Tsuyoshi Yamamoto
CPC classification number: H10N60/805 , H10N60/0912
Abstract: A quantum device capable of suppressing the deterioration of the performance thereof is provided. A quantum device (1) includes a plurality of first conductors (2), a plurality of second conductors (4), and a conductor layer (6). The first conductors (2), the second conductors (4), and the conductor layer (6) are formed of superconducting materials. An oxide film (8) is formed between the first conductors (2) and the second conductors (4). A Josephson junction (10) is formed by a part of one of the plurality of first conductors (2), a part of one of the plurality of second conductors (4), and the oxide film (8). The one first conductor (2) constituting the Josephson junction (10) and the conductor layer (6) are connected to each other directly or through another conductor. The one second conductor (4) constituting the Josephson junction (10) and the conductor layer (6) are connected to each other directly or through another conductor.
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公开(公告)号：US20220239256A1
公开(公告)日：2022-07-28
申请号：US17573841
申请日：2022-01-12
Applicant: NEC Corporation
Inventor： Yoshihito HASHIMOTO , Tsuyoshi Yamamoto , Tomohiro Yamaji
IPC: H03B15/00
Abstract: An oscillator in which crosstalk can be reduced is provided. An oscillator includes a SQUID, a transmission line connected to the SQUID, a ground plane, and a first connection circuit disposed in a vicinity of a node of an electric field of a standing wave that is generated when the oscillator is oscillating, the first connection circuit connecting parts of the ground plane located on both sides of the transmission line to each other.
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公开(公告)号：US20210201188A1
公开(公告)日：2021-07-01
申请号：US17115971
申请日：2020-12-09
Applicant: NEC CORPORATION
Inventor： Tomohiro YAMAJI , Tsuyoshi Yamamoto
Abstract: A resonator, an oscillator, and a quantum computer capable of preventing oscillation conditions for generating a parametric oscillation from becoming complicated are provided. A resonator includes at least one loop circuit in which a first superconducting line, a first Josephson junction, a second superconducting line, and a second Josephson junction are connected in a ring shape, in which critical current values of the first and second Josephson junctions are different from each other.
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