公开(公告)号：US20230237362A1

公开(公告)日：2023-07-27

申请号：US18007769

申请日：2020-06-05

Applicant: NEC Corporation

Inventor： Akira MIYATA ,  Katsumi KIKUCHI ,  Suguru WATANABE ,  Takanori NISHI ,  Hideyuki SATOU ,  Tomohiro YAMAJI ,  Tsuyoshi YAMAMOTO ,  Yoshihito HASHIMOTO

IPC: G06N10/40 ,  G01R33/035

CPC classification number: G06N10/40 ,  G01R33/0354

Abstract: Provided is a quantum device capable of suppressing reduction in performance of quantum bit even when a quantum chip is flip-chip mounted on an interposer. A quantum chip (10) is flip-chip mounted on an interposer (20) by a bump (30). A coplanar line (12) coupling adjacent quantum bits is formed on the quantum chip (10). A gap (22) is provided, in the interposer (20), at a location facing a center conductor (12a) of the coplanar line (12). A second ground electrode (24) is formed around gap (22). The interposer (20) has a connection electrode (40) connecting the second ground electrode (24) around the gap (22). A bump (30A) formed in the vicinity of the connection electrode (40) is connected to the first ground electrode (12b) and the second ground electrode (24).

公开(公告)号：US20250125801A1

公开(公告)日：2025-04-17

申请号：US18783742

申请日：2024-07-25

Applicant: NEC Corporation

Inventor： Aiko YAMAGUCHI ,  Tomohiro YAMAJI ,  Ryoji MIYAZAKI

IPC: H03K17/92 ,  G06N10/40

Abstract: A superconducting quantum circuit apparatus includes: a coupler; a plurality of coupling ports; a plurality of qubits coupled to the coupler via the plurality of coupling ports, respectively; and a reserve port provided as a spare coupling port to be coupled to the coupler, separately from the plurality of coupling ports.

公开(公告)号：US20230142878A1

公开(公告)日：2023-05-11

申请号：US17978356

申请日：2022-11-01

Applicant: NEC Corporation

Inventor： Tomohiro YAMAJI

IPC: G01R33/035 ,  G06N10/40 ,  H01L39/22 ,  H01L27/18 ,  H01L39/02

CPC classification number: G01R33/0354 ,  G06N10/40 ,  H01L39/223 ,  H01L27/18 ,  H01L39/025

Abstract: A superconducting quantum circuit includes a plurality of SQUIDs (Superconducting Quantum Interference Devices) connected in parallel, each of the plurality of SQUIDs including a first superconducting line, a first Josephson junction, a second superconducting line, and a second Josephson junction connected in a loop, wherein a junction area of the first Josephson junction and a junction area of the second Josephson junction are different from each other, the plurality of SQUIDs configured to be mutually different in either one or both of: a sum of the junction area of the first Josephson junction and the junction area of the second Josephson junction; and a ratio of the junction area of the first Josephson junction to the junction area of the second Josephson junction.

公开(公告)号：US20230318601A1

公开(公告)日：2023-10-05

申请号：US18101917

申请日：2023-01-26

Applicant: NEC Corporation

Inventor： Tomohiro YAMAJI ,  Ryoji MIYAZAKI

IPC: H03K17/92 ,  G06N10/20 ,  G06N10/40

CPC classification number: H03K17/92 ,  G06N10/20 ,  G06N10/40

Abstract: A superconducting quantum circuit apparatus includes first through fourth qubits; and a coupler arranged in a region surrounded by a ground plane. The coupler includes: first and second electrodes opposed to each other; and a nonlinear element including at least one Josephson junction bridged between the first electrode and the second electrode between the first and second electrode, the first electrode including first and second opposing portions extended toward the first and second qubits, the second electrode including third and fourth opposing portions extended toward third and fourth qubit, the first through fourth opposing portions having ends for capacitive coupling with the first through fourth qubits, respectively. The ends of the first through fourth opposing portions are disposed within the region surrounded by the ground plane.

公开(公告)号：US20220231216A1

公开(公告)日：2022-07-21

申请号：US17619381

申请日：2020-03-16

Applicant: NEC Corporation

Inventor： Tomohiro YAMAJI ,  Tsuyoshi YAMAMOTO

IPC: H01L39/24 ,  H01L39/22 ,  H01L39/02 ,  H01L27/18

Abstract: A circuit manufacturing method according to the present disclosure is a circuit manufacturing method by deposition, comprising performing first deposition for forming a first superconductor layer, oxidizing a surface of the first superconductor layer to form an oxide film, performing second deposition for forming a second superconductor layer, whereby a circuit in which Josephson junctions are aligned is generated. A mask includes two opening parts and an odd number of first-type opening parts. The width of a first-type opening part has such a length that the area of a Josephson junction formed based on the first superconductor layer and the second superconductor layer derived from the first-type opening part becomes larger than the area of a Josephson junction formed based on the first superconductor layer and the second superconductor layer derived from the two opening parts that are adjacent to each other.

公开(公告)号：US20230163762A1

公开(公告)日：2023-05-25

申请号：US17986031

申请日：2022-11-14

Applicant: NEC Corporation

Inventor： Tomohiro YAMAJI ,  Aiko YAMAGUCHI

IPC: H03K17/92 ,  H03H11/16 ,  G06N10/20

CPC classification number: H03K17/92 ,  H03H11/16 ,  G06N10/20

Abstract: A superconducting quantum circuit apparatus, including: two or four Josephson parametric oscillators, JPOs, each including: a SQUID; and a pump line, with a pump signal supplied thereto, providing a magnetic flux penetrating through the loop of the SQUID, the JPOs oscillating parametrically in response to the pump signal supplied to the pump line; a coupler to couple the two or four JPOs; and a phase adjuster that varies a relative phase between or among pump signals supplied respectively to the pump lines of the two or four JPOs for parametric oscillation, to vary a strength of a two-body or four-body interaction.

公开(公告)号：US20220261676A1

公开(公告)日：2022-08-18

申请号：US17626588

申请日：2020-06-26

Applicant: NEC Corporation

Inventor： Tsuyoshi YAMAMOTO ,  Tomohiro YAMAJI ,  Yoshihito HASHIMOTO

IPC: G06N10/00 ,  H03B15/00 ,  H01L39/22 ,  H03K3/38

Abstract: A resonator, an oscillator, and a quantum computer in which both moderate nonlinearity and a low loss are achieved, and the area occupied by the circuit can be reduced are provided. A resonator (100) includes at least one loop circuit (110) in which a first superconducting line (101), a first Josephson junction (103), a second superconducting line (102), and a second Josephson junction (104) are connected in a ring shape, at least one third Josephson junction (130) provided separately from the Josephson junction included in the loop circuit (110), and a capacitor (120), in which the loop circuit (110), the third Josephson junction (130), and the capacitor (120) are connected in a ring shape.

公开(公告)号：US20220247407A1

公开(公告)日：2022-08-04

申请号：US17626567

申请日：2020-06-26

Applicant: NEC Corporation

Inventor： Tsuyoshi YAMAMOTO ,  Tomohiro YAMAJI ,  Yoshihito HASHIMOTO

IPC: H03K17/92 ,  H03B15/00 ,  G06N10/40

Abstract: A resonator, an oscillator, and a quantum computer in which the area occupied by the circuit can be reduced is provided. A resonator (100) includes a loop circuit (110) in which a first superconducting line (101), a first Josephson junction (103), a second superconducting line (102), and a second Josephson junction (104) are connected in a ring shape, and a capacitor (120). The capacitor (120) and the loop circuit (110) are connected in a ring shape.

公开(公告)号：US20250148665A1

公开(公告)日：2025-05-08

申请号：US18910241

申请日：2024-10-09

Applicant: NEC Corporation

Inventor： Tomohiro YAMAJI ,  Ryoji Miyazaki ,  Yuki Susa

IPC: G06T11/20 ,  G06N10/20

Abstract: A display control device generates data for displaying at least three variable nodes, wherein each variable node indicates a state of each of at least three quantum bit, parity node indicating a parity of the at least three quantum bits, and edges coupling between each variable nodes and the parity node.

公开(公告)号：US20240243082A1

公开(公告)日：2024-07-18

申请号：US18400164

申请日：2023-12-29

Applicant: NEC Corporation

Inventor： Tomohiro YAMAJI ,  Ayuka TADA

IPC: H01L23/00 ,  H10N60/80

CPC classification number: H01L24/05 ,  H01L24/04 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H10N60/80 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/49111 ,  H01L2224/49176

Abstract: Provided is a quantum chip that includes a substrate, a superconducting layer formed on a surface of the substrate, an electrode formed on a surface of the superconducting layer along an outer edge of the substrate, and a periodic structure formed on a surface of the superconducting layer along an outer edge of the substrate.