公开(公告)号：US20140118363A1

公开(公告)日：2014-05-01

申请号：US14043411

申请日：2013-10-01

Applicant: NVIDIA Corporation

Inventor： Ziyad S. HAKURA ,  Jeffrey A. BOLZ ,  Amanpreet GREWAL ,  Matthew JOHNSON ,  Andrei KHODAKOVSKY

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: A method for managing bind-render-target commands in a tile-based architecture. The method includes receiving a requested set of bound render targets and a draw command. The method also includes, upon receiving the draw command, determining whether a current set of bound render targets includes each of the render targets identified in the requested set. The method further includes, if the current set does not include each render target identified in the requested set, then issuing a flush-tiling-unit-command to a parallel processing subsystem, modifying the current set to include each render target identified in the requested set, and issuing bind-render-target commands identifying the requested set to the tile-based architecture for processing. The method further includes, if the current set of render targets includes each render target identified in the requested set, then not issuing the flush-tiling-unit-command.

Abstract translation: 一种在基于瓦片的架构中管理绑定渲染目标命令的方法。 该方法包括接收所请求的一组绑定的渲染目标和绘制命令。 该方法还包括在接收到绘制命令时，确定当前的一组绑定的渲染目标是否包括在所请求的集合中识别的每个渲染目标。 该方法还包括：如果当前集合不包括在所请求的集合中识别的每个呈现目标，则向并行处理子系统发出冲洗平铺单元命令，将当前集合修改为包括在所请求的集合中标识的每个呈现目标 设置并发布将标识所请求的集合的bind-render-target命令发布到基于瓦片的架构以进行处理。 该方法还包括，如果当前呈现目标集合包括在所请求的集合中识别的每个呈现目标，则不发出flush-tiling-unit-command。

公开(公告)号：US20170206623A9

公开(公告)日：2017-07-20

申请号：US14043411

申请日：2013-10-01

Applicant: NVIDIA Corporation

Inventor： Ziyad S. HAKURA ,  Jeffrey A. BOLZ ,  Amanpreet GREWAL ,  Matthew JOHNSON ,  Andrei KHODAKOVSKY

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: A method for managing bind-render-target commands in a tile-based architecture. The method includes receiving a requested set of bound render targets and a draw command. The method also includes, upon receiving the draw command, determining whether a current set of bound render targets includes each of the render targets identified in the requested set. The method further includes, if the current set does not include each render target identified in the requested set, then issuing a flush-tiling-unit-command to a parallel processing subsystem, modifying the current set to include each render target identified in the requested set, and issuing bind-render-target commands identifying the requested set to the tile-based architecture for processing. The method further includes, if the current set of render targets includes each render target identified in the requested set, then not issuing the flush-tiling-unit-command.

公开(公告)号：US20150097847A1

公开(公告)日：2015-04-09

申请号：US14046064

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Jonathan DUNAISKY ,  Henry Packard MORETON ,  Jeffrey A. BOLZ ,  Yury Y. URALSKY ,  James Leroy DEMING ,  Rui M. BASTOS ,  Patrick R. BROWN ,  Amanpreet GREWAL ,  Christian AMSINCK ,  Poornachandra RAO ,  Jerome F. DULUK, JR. ,  Andrew J. TAO

IPC: G09G5/39 ,  G06T1/60

CPC classification number: G09G5/39 ,  G06F12/0897 ,  G06F12/1027 ,  G06T1/60

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Abstract translation: 本发明的一个实施例包括被配置为管理稀疏映射的存储器管理单元（MMU）。 MMU根据指示稀疏状态的页表项（PTE）处理将虚拟地址转换为物理地址的请求。 如果MMU确定PTE不包括从虚拟地址到物理地址的映射，则MMU将根据稀疏状态对该请求进行响应。 如果稀疏状态为活动状态，则MMU将根据请求的类型是否为写入操作确定物理地址，然后生成请求的确认。 相比之下，如果稀疏状态不活动，则MMU会生成页面错误。 有利地，所公开的实施例使得计算机系统能够管理稀疏映射，而不会引起与页面故障和常规的基于软件的稀疏映射管理相关联的性能下降。

公开(公告)号：US20140267375A1

公开(公告)日：2014-09-18

申请号：US14028421

申请日：2013-09-16

Applicant: NVIDIA CORPORATION

Inventor： Mark J. KILGARD ,  Jeffrey A. BOLZ

IPC: G06T3/00

CPC classification number: G06T7/0079 ,  G06T1/20 ,  G06T1/60 ,  G06T3/0012 ,  G06T11/40

Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.

Abstract translation: 本发明的一个实施例包括用于光栅化包括在路径之间共享的边缘的图元的技术。 对于每个边缘，光栅化器单元从多个样本规则中选择并应用样本规则。 如果边缘是共享的，则所选择的样本规则使得与单个颜色样本相关联的每组覆盖样本被视为完全在边缘内部或完全在边缘外部。 因此，当每像素的覆盖样本的数量超过每像素的颜色样本的数量时，引起的接合伪影可能被减少。 在现有技术中，减少这种接合伪影通常涉及增加每像素的颜色样本的数量，以等于每像素的覆盖样本的数量。 有利地，所公开的技术使得能够使用降低颜色与覆盖样本的比率的算法进行渲染，从而减少存储器消耗和存储器带宽使用，而不会引起与共享边缘相关联的协调伪影。

公开(公告)号：US20140118373A1

公开(公告)日：2014-05-01

申请号：US14045361

申请日：2013-10-03

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Cynthia Ann Edgeworth ALLISON ,  Dale L. KIRKLAND ,  Andrei KHODAKOVSKY ,  Jeffrey A. BOLZ

IPC: G09G5/395

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a technique for managing graphics processing resources in a tile-based architecture. The technique includes storing a release packet associated with a graphics processing resource in a buffer and initiating a replay of graphics primitives stored in the buffer and associated with the graphics processing resource. The technique further includes, for each tile included in a plurality of tiles and processed during the replay, reading the release packet and determining whether the tile is a last tile processed during the replay. The technique further includes determining not to transmit the release packet to a screen-space pipeline and continuing to read graphics data stored in the buffer if the tile is not the last tile to be processed during the replay, or transmitting the release packet to the screen-space pipeline if the tile is the last tile to be processed during the replay.

Abstract translation: 本发明的一个实施例提出了一种用于管理基于瓦片的架构中的图形处理资源的技术。 该技术包括将与图形处理资源相关联的释放分组存储在缓冲器中，并且启动存储在缓冲器中并与图形处理资源相关联的图形基元的重放。 该技术还包括对于包括在多个瓦片中并在重放期间被处理的每个瓦片，读取释放分组并确定瓦片是否是在重放期间处理的最后一个瓦片。 该技术还包括确定不将释放分组发送到屏幕空间流水线，并且如果瓦片不是在重放期间要处理的最后一个瓦片，或者将释放分组发送到屏幕，则继续读取存储在缓冲器中的图形数据 如果瓦片是在重放期间要处理的最后一个瓦片，则为 - 空间管道。