公开(公告)号：US20210294791A1

公开(公告)日：2021-09-23

申请号：US16826005

申请日：2020-03-20

Applicant: NVIDIA Corporation

Inventor： Sreedhar Narayanaswamy ,  Shantanu K. Sarangi ,  Hemalkumar Chandrakant Doshi ,  Hari Unni Krishnan ,  Gunaseelan Ponnuvel ,  Brian Lawrence Smith

IPC: G06F16/23

Abstract: Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

公开(公告)号：US09293380B2

公开(公告)日：2016-03-22

申请号：US13663591

申请日：2012-10-30

Applicant: Nvidia Corporation

Inventor： Gunaseelan Ponnuvel

IPC: H01L21/66 ,  G01R31/28

CPC classification number: H01L22/14 ,  G01R31/2831 ,  H01L22/20

Abstract: A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process.

Abstract translation: 一种用于在晶片制造工艺中选择要应用于具有不同电特性的晶体管的比率的降额因子的测试系统和方法。 在一个实施例中，测试系统包括：（1）结构高速自动测试设备（ATE），其可操作以在不同工艺条件下制造的集成电路（IC）样本上以多个时钟频率迭代结构性的速度测试;（2） 耦合到结构速度ATE的降额因子选择电路，并且被配置为采用结构速度测试的结果来识别样品中的性能劣化，所述性能劣化指示在随后的晶片制造过程中采用的降额因子。

公开(公告)号：US20140122005A1

公开(公告)日：2014-05-01

申请号：US13663644

申请日：2012-10-30

Applicant: NVIDIA CORPORATION

Inventor： Craig Nishizaki ,  Peter Hung ,  Gunaseelan Ponnuvel ,  Chien-Hsiung Peng

IPC: G06F19/00 ,  G01R31/26

CPC classification number: G01R31/2894 ,  G01D21/00 ,  G06M11/00 ,  G06Q50/04 ,  G06Q90/00 ,  G07C3/08 ,  Y02P90/30

Abstract: A wafer acceptance test (WAT) system and method that, in one embodiment, includes: (1) a saturation current WAT subsystem operable to generate a weighted standard deviation based on target NMOS and PMOS saturation currents and saturation current WAT results, (2) a wafer IC speed WAT subsystem operable to generate a speed performance probability distribution of wafer ICs based on the weighted standard deviation and speed WAT results, (3) a wafer IC power WAT subsystem operable to employ the speed WAT results and power WAT results to generate a power performance model of wafer ICs, and (4) a yield calculator operable to generate a power performance variance probability distribution of wafer ICs based on the power performance model and the power WAT results, and to employ the speed performance probability distribution and the power performance variance probability distribution to generate the yield forecast with respect to a target performance profile.

Abstract translation: 一种晶片验收测试（WAT）系统和方法，其在一个实施例中包括：（1）饱和电流WAT子系统，其可操作以基于目标NMOS和PMOS饱和电流和饱和电流WAT结果产生加权标准偏差;（2） 晶片IC速度WAT子系统可操作以基于加权的标准偏差和速度WAT产生晶片IC的速度性能概率分布结果;（3）可操作以使用速度WAT结果的晶片IC功率WAT子系统和功率WAT结果产生 晶片IC的功率性能模型，以及（4）可以基于功率性能模型和功率WAT产生晶片IC的功率性能方差概率分布的收益计算器，并且使用速度性能概率分布和功率 性能差异概率分布，以产生关于目标绩效概况的收益率预测。