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    Efficient super-sampling with per-pixel shader threads
    12.
    发明授权
    Efficient super-sampling with per-pixel shader threads 有权
    使用每像素着色器线程进行高效超采样

    公开(公告)号：US09495721B2

    公开(公告)日：2016-11-15

    申请号：US13725782

    申请日：2012-12-21

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. Duluk, Jr. ,  Rouslan Dimitrov ,  Eric Lum ,  Rui Bastos

    IPC: G06T1/20 ,  G06T15/00

    CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005 ,  G06T2210/52

    Abstract: Techniques for dispatching pixel information in a graphics processing pipeline. A fragment processing unit generates a pixel that includes multiple samples based on a first portion of a graphics primitive received by a first thread. The fragment processing unit calculates a first value for the first pixel, where the first value is calculated only once for the pixel. The fragment processing unit calculates a first set of values for the samples, where each value in the first set of values corresponds to a different sample and is calculated only once for the corresponding sample. The fragment processing unit combines the first value with each value in the first set of values to create a second set of values. The fragment processing unit creates one or more dispatch messages to store the second set of values in a set of output registers.

    Abstract translation: 在图形处理流水线中调度像素信息的技术。 片段处理单元基于由第一线程接收的图形原语的第一部分生成包括多个样本的像素。 片段处理单元计算第一像素的第一值，其中第一值仅针对像素计算一次。 片段处理单元计算样本的第一组值，其中第一组值中的每个值对应于不同的样本，并且对于相应样本仅计算一次。 片段处理单元将第一值与第一组值中的每个值组合以创建第二组值。 片段处理单元创建一个或多个调度消息以将第二组值存储在一组输出寄存器中。

    DYNAMICALLY REDUCING LATENCY IN PROCESSING PIPELINES
    14.
    发明申请
    DYNAMICALLY REDUCING LATENCY IN PROCESSING PIPELINES 有权

    公开(公告)号：US20230087268A1

    公开(公告)日：2023-03-23

    申请号：US17448258

    申请日：2021-09-21

    Applicant: NVIDIA Corporation

    Inventor： Sau Yan Keith Li ,  Seth Schneider ,  Cody Robson ,  Lars Nordskog ,  Charles Hansen ,  Rouslan Dimitrov

    IPC: G06T1/20 ,  G06F9/48 ,  G06F9/38

    Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.

    Scheduling cache traffic in a tile-based architecture
    15.
    发明授权
    Scheduling cache traffic in a tile-based architecture 有权

    公开(公告)号：US11107176B2

    公开(公告)日：2021-08-31

    申请号：US14043461

    申请日：2013-10-01

    Applicant: NVIDIA Corporation

    Inventor： Ziyad S. Hakura ,  Rouslan Dimitrov

    IPC: G06T1/20 ,  G06T15/20 ,  G06T1/60 ,  G06T15/00 ,  G06F12/0875 ,  G06T15/40 ,  G06F9/38 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/0808 ,  G06F9/44 ,  G06T15/80 ,  G06T17/20

    Abstract: A tile-based system for processing graphics data. The tile based system includes a first screen-space pipeline, a cache unit, and a first tiling unit. The first tiling unit is configured to transmit a first set of primitives that overlap a first cache tile and a first prefetch command to the first screen-space pipeline for processing, and transmit a second set of primitives that overlap a second cache tile to the first screen-space pipeline for processing. The first prefetch command is configured to cause the cache unit to fetch data associated with the second cache tile from an external memory unit. The first tiling unit may also be configured to transmit a first flush command to the screen-space pipeline for processing with the first set of primitives. The first flush command is configured to cause the cache unit to flush data associated with the first cache tile.

    ADAPTIVE UPSCALING OF CLOUD RENDERED GRAPHICS
    20.
    发明申请
    ADAPTIVE UPSCALING OF CLOUD RENDERED GRAPHICS 审中-公开

    公开(公告)号：US20190342555A1

    公开(公告)日：2019-11-07

    申请号：US15967645

    申请日：2018-05-01

    Applicant: Nvidia Corporation

    Inventor： Rouslan Dimitrov ,  Chris Amsinck ,  Viktor Vandanov ,  Santanu Dutta ,  Walter Donovan ,  Olivier Lapicque

    IPC: H04N19/127 ,  H04N19/182 ,  H04N19/194

    Abstract: The present disclosure is directed to a method to increase virtual machine density on a server system through adaptive rendering by dynamically determining when to shift video rendering tasks between the server system and a client computing device. In another embodiment, the adaptive rendering, using various parameters, can select one or more encoding and compression algorithms to use to prepare and process the video for transmission to the client computing device. In another embodiment, a video rendering system is disclosed that can adaptively alter how and where a video is rendered, encoded, and compressed.

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