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公开(公告)号：US12130687B2
公开(公告)日：2024-10-29
申请号：US17961440
申请日：2022-10-06
Applicant: NVIDIA CORPORATION
Inventor： Thomas E. Dewey , Michael Irwin , Simon Lai , Sau Yan Keith Li
IPC: G06F1/00 , G05B13/02 , G06F1/20 , G06F1/3234 , G06F1/324 , G06F1/3287
CPC classification number: G06F1/3234 , G05B13/028 , G06F1/20 , G06F1/206 , G06F1/324 , G06F1/3287
Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.
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公开(公告)号：US20220222783A1
公开(公告)日：2022-07-14
申请号：US17706473
申请日：2022-03-28
Applicant: NVIDIA Corporation
Inventor： Thomas Albert Petersen , Ankan Banerjee , Shishir Goyal , Sau Yan Keith Li , Lars Nordskog , Rouslan Dimitrov
Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.
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公开(公告)号：US12056854B2
公开(公告)日：2024-08-06
申请号：US17706473
申请日：2022-03-28
Applicant: NVIDIA Corporation
Inventor： Thomas Albert Petersen , Ankan Banerjee , Shishir Goyal , Sau Yan Keith Li , Lars Nordskog , Rouslan Dimitrov
CPC classification number: G06T5/70 , G06F9/3877 , G06T1/20 , G06T13/00 , G06T13/20 , G06T15/005 , G09G5/00
Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.
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公开(公告)号：US20240202860A1
公开(公告)日：2024-06-20
申请号：US18594099
申请日：2024-03-04
Applicant: NVIDIA Corporation
Inventor： Sau Yan Keith Li , Seth Schneider , Cody Robson , Lars Nordskog , Charles Hansen , Rouslan Dimitrov
CPC classification number: G06T1/20 , G06F9/3836 , G06F9/4881
Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.
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公开(公告)号：US11784906B2
公开(公告)日：2023-10-10
申请号：US16893327
申请日：2020-06-04
Applicant: NVIDIA CORPORATION
Inventor： Joohwan Kim , Benjamin Boudaoud , Josef B. Spjut , Morgan S. McGuire , Seth P. Schneider , Rouslan L. Dimitrov , Lars Nordskog , Cody J. Robson , Sau Yan Keith Li , Gerrit Ary Slavenburg , Tom J. Verbeure
IPC: H04L43/106 , H04L43/0852 , G06F3/14 , G09G5/14 , G06T1/20
CPC classification number: H04L43/106 , G06F3/14 , G06T1/20 , G09G5/14 , H04L43/0852 , G09G2340/0407
Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.
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Patent Agency Ranking
公开(公告)号：US11700402B1
公开(公告)日：2023-07-11
申请号：US17704732
申请日：2022-03-25
Applicant: NVIDIA Corporation
Inventor： Rouslan Dimitrov , Viktor Grigoryevich Vandanov , Sau Yan Keith Li , James Howard , Scott Phillip Cutler
IPC: H04N21/238 , H04N21/24
CPC classification number: H04N21/23805 , H04N21/2401
Abstract: A performance metrics of a receiver is obtained using frames of an application hosted by a server that are received via a network. The one or more performance metrics include information indicative of a current occupancy of a frame buffer corresponding to the receiver and information indicative of a target occupancy of the frame buffer corresponding to the receiver. The frame buffer of the receiver is used to queue frames of the application for display. A frame rate associated with rendering at least one next frame of the application is adjusted using the one or more performance metrics of the receiver to control population of the frame buffer. Subsequent frames of the application hosted by the server are rendered using the adjusted frame rate. Upon rendering the subsequent frames, the server sends the subsequent frames to the receiver for display.
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公开(公告)号：US11886262B2
公开(公告)日：2024-01-30
申请号：US17306654
申请日：2021-05-03
Applicant: NVIDIA Corporation
Inventor： Sau Yan Keith Li , Thomas E. Dewey , Arthur Chen , Simon Lai , Amit Pabalkar , Santosh Nayak
IPC: G06F1/00 , G06F1/26 , G06F9/4401 , G06F1/08
CPC classification number: G06F1/26 , G06F1/08 , G06F9/4411
Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
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公开(公告)号：US11321816B2
公开(公告)日：2022-05-03
申请号：US17178078
申请日：2021-02-17
Applicant: NVIDIA Corporation
Inventor： Thomas Albert Petersen , Ankan Banerjee , Shishir Goyal , Sau Yan Keith Li , Lars Nordskog , Rouslan Dimitrov
Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.
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9.发明申请公开(公告)号：US20190172181A1
公开(公告)日：2019-06-06
申请号：US16208390
申请日：2018-12-03
Applicant: NVIDIA CORPORATION
Inventor： Thomas Albert Petersen , Ankan Banerjee , Shishir Goyal , Sau Yan Keith Li , Lars Nordskog , Rouslan Dimitrov
Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.
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公开(公告)号：US11922533B2
公开(公告)日：2024-03-05
申请号：US17448258
申请日：2021-09-21
Applicant: NVIDIA Corporation
Inventor： Sau Yan Keith Li , Seth Schneider , Cody Robson , Lars Nordskog , Charles Hansen , Rouslan Dimitrov
CPC classification number: G06T1/20 , G06F9/3836 , G06F9/4881
Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.
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