公开(公告)号：US11379708B2

公开(公告)日：2022-07-05

申请号：US16514078

申请日：2019-07-17

Applicant: NVIDIA Corporation

Inventor： Sachin Idgunji ,  Ming Y. Siu ,  Alex Gu ,  James Reilley ,  Manan Patel ,  Rajeshwaran Selvanesan ,  Ewa Kubalska

IPC: G06F9/30 ,  G06N3/04 ,  G06N3/08 ,  G06F9/38 ,  G06F1/3206

Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), includes a dynamic power controller for adjusting operating voltage and/or frequency. The controller may receive current power used by the integrated circuit and a predicted power determined based on instructions pending in a plurality of processors. The controller determines adjustments that need to be made to the operating voltage and/or frequency to minimize the difference between the current power and the predicted power. An in-system reinforced learning mechanism is included to self-tune parameters of the controller.

公开(公告)号：US12124346B2

公开(公告)日：2024-10-22

申请号：US18068666

申请日：2022-12-20

Applicant: NVIDIA Corporation

Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

IPC: G06F11/267 ,  G06F1/3296 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273

CPC classification number: G06F11/267 ,  G06F1/3296 ,  G06F11/2236 ,  G06F11/27 ,  G06F11/2733

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

公开(公告)号：US20220114069A1

公开(公告)日：2022-04-14

申请号：US17556473

申请日：2021-12-20

Applicant: NVIDIA Corporation

Inventor： Jonah ALBEN ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

IPC: G06F11/267 ,  G06F11/22 ,  G06F1/3296 ,  G06F11/273 ,  G06F11/27

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

公开(公告)号：US20210286693A1

公开(公告)日：2021-09-16

申请号：US16818327

申请日：2020-03-13

Applicant: NVIDIA Corporation

Inventor： Jonah ALBEN ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

IPC: G06F11/267 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273 ,  G06F1/3296

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

公开(公告)号：US11003238B2

公开(公告)日：2021-05-11

申请号：US15583872

申请日：2017-05-01

Applicant: NVIDIA Corporation

Inventor： Anand Shanmugam Sundararajan ,  Ramachandiran V ,  Abhijeet Chandratre ,  Lordson Yue ,  Archana Srinivasaiah ,  Sachin Idgunji

IPC: G06F1/3234

Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.

公开(公告)号：US09195434B2

公开(公告)日：2015-11-24

申请号：US14154463

申请日：2014-01-14

Applicant: Nvidia Corporation

Inventor： Sachin Idgunji

IPC: G06F7/58 ,  G06F1/26

CPC classification number: G06F7/588 ,  G06F1/26

Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.

Abstract translation: 一个真正的随机数发生器，一个产生真实随机数的方法，以及一个结合发生器或方法的系统。 在一个实施例中，发电机包括：（1）环形振荡器，其包括具有电力输入的反相门和（2）耦合到功率输入的时变电源，以向其提供电力，并且包括能够扰乱所提供的功率的功率扰动电路 至少一个电源输入。