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    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME
    2.
    发明申请
    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME 有权

    公开(公告)号：US20240419568A1

    公开(公告)日：2024-12-19

    申请号：US18815553

    申请日：2024-08-26

    Applicant: NVIDIA Corporation

    Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC: G06F11/267 ,  G06F1/3296 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273

    Abstract: In various examples, one or more components or regions of a processing unit-such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    POWER SUPPLY FOR RING-OSCILLATOR BASED TRUE RANDOM NUMBER GENERATOR AND METHOD OF GENERATING TRUE RANDOM NUMBERS
    4.
    发明申请
    POWER SUPPLY FOR RING-OSCILLATOR BASED TRUE RANDOM NUMBER GENERATOR AND METHOD OF GENERATING TRUE RANDOM NUMBERS 有权
    基于振荡器的真正随机数发生器的电源和产生真实随机数的方法

    公开(公告)号：US20150199176A1

    公开(公告)日：2015-07-16

    申请号：US14154463

    申请日：2014-01-14

    Applicant: Nvidia Corporation

    Inventor： Sachin Idgunji

    IPC: G06F7/58 ,  G06F1/26

    CPC classification number: G06F7/588 ,  G06F1/26

    Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.

    Abstract translation: 一个真正的随机数发生器，一个产生真实随机数的方法，以及一个结合发生器或方法的系统。 在一个实施例中，发电机包括：（1）环形振荡器，其包括具有电力输入的反相门和（2）耦合到功率输入的时变电源，以向其提供电力，并且包括能够扰乱所提供的功率的功率扰动电路 至少一个电源输入。

    Leveraging low power states for fault testing of processing cores at runtime
    6.
    发明授权
    Leveraging low power states for fault testing of processing cores at runtime 有权

    公开(公告)号：US11204849B2

    公开(公告)日：2021-12-21

    申请号：US16818327

    申请日：2020-03-13

    Applicant: NVIDIA Corporation

    Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC: G06F11/267 ,  G06F11/22 ,  G06F11/273 ,  G06F11/27 ,  G06F1/3296

    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME
    9.
    发明申请
    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME 有权

    公开(公告)号：US20230123956A1

    公开(公告)日：2023-04-20

    申请号：US18068666

    申请日：2022-12-20

    Applicant: NVIDIA Corporation

    Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC: G06F11/267 ,  G06F11/22 ,  G06F1/3296 ,  G06F11/273 ,  G06F11/27

    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    Leveraging low power states for fault testing of processing cores at runtime
    10.
    发明授权
    Leveraging low power states for fault testing of processing cores at runtime 有权

    公开(公告)号：US11573872B2

    公开(公告)日：2023-02-07

    申请号：US17556473

    申请日：2021-12-20

    Applicant: NVIDIA Corporation

    Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC: G06F11/267 ,  G06F11/22 ,  G06F11/273 ,  G06F11/27 ,  G06F1/3296

    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

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