公开(公告)号：US12019498B2

公开(公告)日：2024-06-25

申请号：US16175232

申请日：2018-10-30

Applicant: NVIDIA Corporation

Inventor： Thomas E. Dewey ,  Narayan Kulshrestha ,  Ramachandiran V ,  Sachin Idgunji ,  Lordson Yue

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/42 ,  G06F15/78 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F1/3278 ,  G06F1/3296 ,  G06F13/4221 ,  G06F15/7807 ,  G06T1/20 ,  G06T15/005 ,  G06F2213/0026

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

公开(公告)号：US11003238B2

公开(公告)日：2021-05-11

申请号：US15583872

申请日：2017-05-01

Applicant: NVIDIA Corporation

Inventor： Anand Shanmugam Sundararajan ,  Ramachandiran V ,  Abhijeet Chandratre ,  Lordson Yue ,  Archana Srinivasaiah ,  Sachin Idgunji

IPC: G06F1/3234

Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.