公开(公告)号：US20100052062A1

公开(公告)日：2010-03-04

申请号：US12502008

申请日：2009-07-13

申请人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

发明人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

摘要翻译： 提供能提高半导体器件的可靠性的半导体器件的制造方法。 用于覆盖形成在半导体衬底中的半导体元件的第一绝缘膜通过具有良好嵌入特性的热CVD法等形成。 通过等离子体CVD法形成第二绝缘膜以覆盖第一绝缘膜，其具有优异的耐湿性。 形成插塞以穿透第一绝缘膜和第二绝缘膜。 在第二绝缘膜上形成由具有较低介电常数的低k膜构成的第三绝缘膜。 通过镶嵌技术在第三绝缘膜中形成布线以与插头电耦合。

公开(公告)号：US06734489B2

公开(公告)日：2004-05-11

申请号：US10122387

申请日：2002-04-16

申请人： Noboru Morimoto ,  Kinya Goto ,  Masahiro Matsumoto

发明人： Noboru Morimoto ,  Kinya Goto ,  Masahiro Matsumoto

IPC分类号： H01L2708

CPC分类号： H01L23/5223 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76838 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A second-level wire is formed by a dual damascene process in a insulating film. In an upper surface of the first insulating film a metal film is formed and serves as a first electrode of an MIM-type capacitor. A second insulating films has a structure in which a plurality of insulating films are layered on a second interconnection layer, in this order. In a first insulating film of the plurality of insulating films, a second electrode of the MIM-type capacitor is formed. The second electrode has a first metal film formed on a second insulating film of the plurality of the insulating films and a second metal film is formed on the first metal film. A portion of the second insulating film which is sandwiched between the first electrode and the second electrode of the MIM-type capacitor serves as a capacitor dielectric film of the MIM-type capacitor. In the second insulating film, a third-level wire is formed Thus, a semiconductor device and a method of manufacturing the same are provided such that the MIM-type capacitor is formed together with metal wires with no additional complicated step.

摘要翻译： 二级线由绝缘膜中的双镶嵌工艺形成。 在第一绝缘膜的上表面形成有金属膜，作为MIM型电容器的第一电极。 第二绝缘膜具有这样的结构，其中多个绝缘膜依次层叠在第二互连层上。 在多个绝缘膜的第一绝缘膜中形成MIM型电容器的第二电极。 第二电极具有形成在多个绝缘膜的第二绝缘膜上的第一金属膜，并且在第一金属膜上形成第二金属膜。 夹在MIM型电容器的第一电极和第二电极之间的第二绝缘膜的一部分用作MIM型电容器的电容器电介质膜。 在第二绝缘膜中，形成第三级线。因此，提供半导体器件及其制造方法，使得MIM型电容器与金属线一起形成，而不需要额外的复杂步骤。

公开(公告)号：US20060103025A1

公开(公告)日：2006-05-18

申请号：US11271811

申请日：2005-11-14

申请人： Takeshi Furusawa ,  Masahiro Matsumoto ,  Noboru Morimoto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Masahiro Matsumoto ,  Noboru Morimoto ,  Masazumi Matsuura

IPC分类号： H01L23/52

CPC分类号： H01L23/585 ,  H01L23/3157 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a low dielectric constant film having a copper interconnection formed therein, a silicon oxide film arranged above the low dielectric constant film, a surface protection film arranged above the silicon oxide film, a sealing ring formed to surround a circuit forming region, and a groove portion formed outside the sealing ring when viewed two-dimensionally. The groove portion is formed such that its bottom portion is located above the low dielectric constant film and such that the bottom portion is located below an upper end of the copper interconnection.

摘要翻译： 半导体器件包括其中形成有铜互连的低介电常数膜，布置在低介电常数膜上的氧化硅膜，设置在氧化硅膜上方的表面保护膜，形成为围绕电路形成区的密封环， 以及当二维地观察时形成在密封环的外侧的槽部。 槽部形成为使其底部位于低介电常数膜的上方，并且使得底部位于铜互连的上端下方。

公开(公告)号：US06509648B1

公开(公告)日：2003-01-21

申请号：US09691030

申请日：2000-10-19

申请人： Noboru Morimoto ,  Masazumi Matsuura ,  Kinya Goto

发明人： Noboru Morimoto ,  Masazumi Matsuura ,  Kinya Goto

IPC分类号： H01L2144

CPC分类号： H01L21/76819

摘要： A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 Hm over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG. 5 is dipped in the above-mentioned ammonia hydrogen peroxide mixture for 60 seconds to clean the surface of the interlayer dielectric film (50).

摘要翻译： 获得制造半导体器件的方法，即使通过制造步骤的变化使FSG膜的上表面的一部分露出，也能够避免在上布线层中的布线之间的短路的产生。 在USG膜（4）在FSG膜（3）的整个表面上沉积厚度为1m的USG膜（4）之后，将USG膜（4）从其上表面抛光并去除900nm的厚度， CMP方法。 此时，FSG膜（3）的上表面的一部分通过生产步骤的变化而暴露。 接下来，用对FSG膜（3）的蚀刻速率和对USG膜（5）的蚀刻速率基本相同的清洗液清洁层间绝缘膜（50）的表面。 这样的清洗液可以是例如NH 4 OH:H 2 O 2 :H 2 O = 1：1：20的氨过氧化氢混合物。 图1所示的结构 5浸渍在上述氨过氧化氢混合物中60秒以清洁层间电介质膜（50）的表面。