公开(公告)号：US20060103025A1

公开(公告)日：2006-05-18

申请号：US11271811

申请日：2005-11-14

申请人： Takeshi Furusawa ,  Masahiro Matsumoto ,  Noboru Morimoto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Masahiro Matsumoto ,  Noboru Morimoto ,  Masazumi Matsuura

IPC分类号： H01L23/52

CPC分类号： H01L23/585 ,  H01L23/3157 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a low dielectric constant film having a copper interconnection formed therein, a silicon oxide film arranged above the low dielectric constant film, a surface protection film arranged above the silicon oxide film, a sealing ring formed to surround a circuit forming region, and a groove portion formed outside the sealing ring when viewed two-dimensionally. The groove portion is formed such that its bottom portion is located above the low dielectric constant film and such that the bottom portion is located below an upper end of the copper interconnection.

摘要翻译： 半导体器件包括其中形成有铜互连的低介电常数膜，布置在低介电常数膜上的氧化硅膜，设置在氧化硅膜上方的表面保护膜，形成为围绕电路形成区的密封环， 以及当二维地观察时形成在密封环的外侧的槽部。 槽部形成为使其底部位于低介电常数膜的上方，并且使得底部位于铜互连的上端下方。

公开(公告)号：US06737319B2

公开(公告)日：2004-05-18

申请号：US10300579

申请日：2002-11-21

申请人： Noboru Morimoto ,  Masazumi Matsuura ,  Kinya Goto

发明人： Noboru Morimoto ,  Masazumi Matsuura ,  Kinya Goto

IPC分类号： H01L218242

CPC分类号： H01L21/76819

摘要： A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG. 5 is dipped in the above-mentioned ammonia hydrogen peroxide mixture for 60 seconds to clean the surface of the interlayer dielectric film (50).

摘要翻译： 获得制造半导体器件的方法，即使通过制造步骤的变化使FSG膜的上表面的一部分露出，也能够避免在上布线层中的布线之间的短路的产生。 在USG膜（4）在FSG膜（3）的整个表面上沉积1μm的厚度之后，USG膜（4）从上表面抛光并去除900nm的厚度， CMP方法。 此时，FSG膜（3）的上表面的一部分通过制造工序的变形而露出。 接下来，用对FSG膜（3）的蚀刻速率和对USG膜（5）的蚀刻速率基本相同的清洗液清洁层间绝缘膜（50）的表面。 这样的清洗液可以是例如NH 4 OH:H 2 O 2 :H 2 O = 1：1：20的氨过氧化氢混合物。 图1所示的结构 5浸渍在上述氨过氧化氢混合物中60秒以清洁层间电介质膜（50）的表面。

公开(公告)号：US20110215447A1

公开(公告)日：2011-09-08

申请号：US13112738

申请日：2011-05-20

申请人： Takeshi Furusawa ,  Norio Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Norio Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件 环在芯片角附近包括向内突出形式的密封环突出部。

公开(公告)号：US08963291B2

公开(公告)日：2015-02-24

申请号：US13112738

申请日：2011-05-20

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/56

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件 环在芯片角附近包括向内突出形式的密封环突出部。

公开(公告)号：US08018030B2

公开(公告)日：2011-09-13

申请号：US12410170

申请日：2009-03-24

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/56

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁 并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

公开(公告)号：US07960279B2

公开(公告)日：2011-06-14

申请号：US12493347

申请日：2009-06-29

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

摘要翻译： 在半导体衬底上具有多层布线结构器件的半导体中，多层布线结构包括至少具有有机硅氧烷绝缘膜的层间绝缘膜。 有机硅氧烷绝缘膜的相对介电常数为3.1以下，硬度为2.7GPa以上，碳原子与硅原子的比例在0.5以上且1.0以下。 此外，多层布线结构可以包括碳原子与硅原子之比不大于0.1的绝缘层，绝缘层由有机硅氧烷绝缘膜的碳离子形成在有机硅氧烷绝缘膜的顶表面上 电影。

公开(公告)号：US20070114668A1

公开(公告)日：2007-05-24

申请号：US11561629

申请日：2006-11-20

申请人： Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

发明人： Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/00015

摘要： A semiconductor device is equipped with a semiconductor chip which has at least one layer of first insulating film formed on a substrate, and a plurality of pads arranged on a layer higher than the first insulating film. The plurality of pads on the semiconductor chip are arranged parallel to a predetermined chip edge of the semiconductor chip. The first insulating film has a reinforcement pattern in a region underneath each of the plurality of pads. In the region underneath each pad, occupancy of the reinforcement pattern in the first insulating film is within a predetermined range permitted for the region underneath each pad and occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction perpendicular to the predetermined chip edge is higher than occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction parallel to the chip edge.

摘要翻译： 半导体器件配备有半导体芯片，该半导体芯片具有形成在基板上的至少一层第一绝缘膜，以及布置在高于第一绝缘膜的层上的多个焊盘。 半导体芯片上的多个焊盘平行于半导体芯片的预定的芯片边缘布置。 第一绝缘膜在多个焊盘中的每一个下方的区域中具有加强图案。 在每个垫下面的区域中，第一绝缘膜中的加强图案的占用在每个垫下面的区域允许的预定范围内，并且在加强图案布置在一排中的整个区域中的加强图案的占用 在垂直于预定芯片边缘的方向上的线在高于在与芯片边缘平行的方向上排列成一列的行的整个区域中的加强图案的占有率高。

公开(公告)号：US06399424B1

公开(公告)日：2002-06-04

申请号：US09663201

申请日：2000-09-18

申请人： Masazumi Matsuura ,  Kinya Goto ,  Noboru Morimoto

发明人： Masazumi Matsuura ,  Kinya Goto ,  Noboru Morimoto

IPC分类号： H01L2144

CPC分类号： H01L21/76811 ,  H01L21/76801 ,  H01L21/76813 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Implemented is a method of manufacturing a contact structure having a combination of formation of a buried wiring and that of a low dielectric constant interlayer insulating film in which a connecting hole to be formed in a low dielectric constant interlayer insulating film does not turn into an abnormal shape. A fourth interlayer insulating film 11 is formed on an upper surface of a third interlayer insulating film 10. Next, patterning for a wiring trench and a connecting hole is carried out into the fourth interlayer insulating film 11 and the third interlayer insulating film 10, respectively. Then, a pattern of the connecting hole is first formed in a third low dielectric constant interlayer insulating film 9. Thereafter, a second interlayer insulating film 8 exposed in the pattern is removed and a pattern of the wiring trench is formed in the third interlayer insulating film 10. Subsequently, second and third low dielectric constant interlayer insulating films 7 and 9 are etched, and the wiring trench and the connecting hole are formed at the same time. Thus, a photoresist can be formed again without the second and third low dielectric constant interlayer insulating films 7 and 9 exposed, and an abnormal shape is generated in the connecting hole with difficulty.

摘要翻译： 具体实施方式是制造具有掩埋布线的形成和低介电常数层间绝缘膜的组合的接触结构的方法，其中形成在低介电常数层间绝缘膜中的连接孔不会变成异常 形状。 第四层间绝缘膜11形成在第三层间绝缘膜10的上表面上。接下来，分别对第四层间绝缘膜11和第三层间绝缘膜10进行布线沟槽和连接孔的图案化 。 然后，首先在第三低介电常数层间绝缘膜9中形成连接孔的图案。然后，去除以图案露出的第二层间绝缘膜8，并且在第三层间绝缘层中形成布线沟槽的图案 随后，蚀刻第二和第三低介电常数层间绝缘膜7和9，并且同时形成布线沟槽和连接孔。 因此，可以再次形成光致抗蚀剂，而不会使第二和第三低介电常数层间绝缘膜7和9暴露，并且难以在连接孔中产生异常形状。

公开(公告)号：US20090263963A1

公开(公告)日：2009-10-22

申请号：US12493347

申请日：2009-06-29

申请人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

摘要翻译： 在半导体衬底上具有多层布线结构器件的半导体中，多层布线结构包括至少具有有机硅氧烷绝缘膜的层间绝缘膜。 有机硅氧烷绝缘膜的相对介电常数为3.1以下，硬度为2.7GPa以上，碳原子与硅原子的比例在0.5以上且1.0以下。 此外，多层布线结构可以包括碳原子与硅原子之比不大于0.1的绝缘层，绝缘层由有机硅氧烷绝缘膜的碳离子形成在有机硅氧烷绝缘膜的顶表面上 电影。

公开(公告)号：US20090189245A1

公开(公告)日：2009-07-30

申请号：US12410170

申请日：2009-03-24

申请人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁 并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。