公开(公告)号：US06633926B1

公开(公告)日：2003-10-14

申请号：US09450873

申请日：1999-11-29

申请人： Masaaki Harada ,  Tsutomu Sekibe

发明人： Masaaki Harada ,  Tsutomu Sekibe

IPC分类号： G06F1300

CPC分类号： G06F13/28

摘要： A DMA transfer device transfers data from a first region to a second region in a memory allowing high-speed page access. The DMA transfer device includes: a first detecting unit for detecting a plurality of read areas that form the first region, each read area being located between page boundaries; a second detecting unit for detecting a plurality of write areas that form the second region, each write area being located between page boundaries; and an access unit for performing high-speed page access to each of the read areas and each of the write areas.

摘要翻译： DMA传输设备将数据从第一区域传送到允许高速页面访问的存储器中的第二区域。 DMA传送装置包括：第一检测单元，用于检测形成第一区域的多个读取区域，每个读取区域位于页面边界之间; 第二检测单元，用于检测形成第二区域的多个写入区域，每个写入区域位于页面边界之间; 以及用于对每个读取区域和每个写入区域执行高速页面访问的访问单元。

公开(公告)号：US07793083B2

公开(公告)日：2010-09-07

申请号：US11667762

申请日：2005-11-24

申请人： Masaaki Harada ,  Tsutomu Sekibe

发明人： Masaaki Harada ,  Tsutomu Sekibe

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/105 ,  G06F21/6227 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2137

摘要： A processor (10) manages, in an instruction management unit (103) and a data attribute management unit (105), secure attributes indicating whether instruction code and data stored in an instruction cache (102) and a data cache (104) of the processor (10) are confidential information. When the instruction code and the data are confidential information, the processor (10) also manages secure processing identification information for indicating in which secure process the confidential information is to be used. When the operating mode is switched from the secure mode to the normal mode, only the confidential information is disabled by a memory disabling unit (108). This prevents confidential information from being analyzed by the processor in the normal mode.

摘要翻译： 处理器（10）在指令管理单元（103）和数据属性管理单元（105）中管理指示存储在指令高速缓存（102）和数据高速缓存（104）中的指令代码和数据的安全属性 处理器（10）是机密信息。 当指令代码和数据是机密信息时，处理器（10）还管理安全处理识别信息，用于指示在哪个安全处理中使用机密信息。 当操作模式从安全模式切换到正常模式时，只有秘密信息被存储器禁用单元（108）禁用。 这防止在正常模式下由处理器分析机密信息。

公开(公告)号：US06225916B1

公开(公告)日：2001-05-01

申请号：US09127376

申请日：1998-07-31

申请人： Hiroko Sugimoto ,  Tsutomu Sekibe ,  Hideyuki Kanzaki ,  Tomohiko Kitamura

发明人： Hiroko Sugimoto ,  Tsutomu Sekibe ,  Hideyuki Kanzaki ,  Tomohiko Kitamura

IPC分类号： H04Q700

CPC分类号： G08C19/28 ,  G08C25/00

摘要： The remote control signal reception controller receives control data transmitted from a remote control signal sender. The remote control signal reception controller informs a CPU that controls a device of the information on the received control data by interrupting the CPU. When doing so, the remote control signal reception controller judges whether a piece of control data that has just been received and a preceding piece of control data were consecutively transmitted, and whether these two pieces of control data are the same control data. The remote control signal reception controller interrupts the CPU only once when finding that the same control data is continuously transmitted as the result of this judgement.

摘要翻译： 遥控信号接收控制器接收从遥控信号发送器发送的控制数据。 遥控信号接收控制器通过中断CPU来通知CPU控制所接收的控制数据的信息的装置。 当这样做时，遥控信号接收控制器判断是否连续发送了刚刚接收到的一条控制数据和前一条控制数据，以及这两条控制数据是否是相同的控制数据。 作为判断结果，当发现连续发送相同的控制数据时，遥控信号接收控制器仅中断CPU一次。

公开(公告)号：US5579500A

公开(公告)日：1996-11-26

申请号：US200217

申请日：1994-02-23

申请人： Tsutomu Sekibe ,  Tomohiko Kitamura ,  Toshiyuki Ochiai

发明人： Tsutomu Sekibe ,  Tomohiko Kitamura ,  Toshiyuki Ochiai

IPC分类号： G06F12/02

CPC分类号： G06F12/0215

摘要： An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes an data storage device for preserving data corresponding to a predetermined address; a judging device for judging whether an access address indicated by the access request matches the predetermined address; and a control device for making the data storage device output data preserved therein to the system bus when the access address has been judged to match the predetermined address, and for making the data storage device hold data corresponding to a next address subsequent to the access address when the access address has been judged not to match the predetermined address.

摘要翻译： 响应于通过系统总线发送的访问请求，控制对存储器的数据读取访问的装置和方法。 该装置包括用于保存对应于预定地址的数据的数据存储装置; 用于判断由所述访问请求指示的访问地址是否匹配所述预定地址的判断装置; 以及控制装置，用于当访问地址已经被判定为与预定地址相匹配时，用于使数据存储装置输出保存在其中的数据到系统总线，并且使得数据存储装置保持对应于访问地址之后的下一个地址的数据 当访问地址被判定为不符合预定地址时。

公开(公告)号：US08520563B2

公开(公告)日：2013-08-27

申请号：US12995558

申请日：2009-05-29

申请人： Tadashi Ono ,  Isao Kato ,  Hideyuki Yamada ,  Shinichiro Nishioka ,  Hiroshi Suenaga ,  Tsutomu Sekibe

发明人： Tadashi Ono ,  Isao Kato ,  Hideyuki Yamada ,  Shinichiro Nishioka ,  Hiroshi Suenaga ,  Tsutomu Sekibe

IPC分类号： H04B1/44

CPC分类号： H04L5/16 ,  H04L5/18 ,  H04L25/14

摘要： A host device and a slave device are set to a full-duplex mode by temporarily switching the communication direction of a first transmission channel or a second transmission channel after completing transmission and reception of a predetermined number of data packets in the half-duplex mode. The host device or the slave device can thus transmit an interrupt request, such as a request associated with a wait status or a busy status, to its communication target using the temporary full-duplex mode. This enables the host device or the slave device to process such an interrupt request during high-speed data transfer performed in the half-duplex mode.

摘要翻译： 在半双工模式下完成预定数量的数据分组的发送和接收之后，通过临时切换第一传输信道或第二传输信道的通信方向，将主机设备和从设备设置为全双工模式。 因此主机设备或从设备可以使用临时全双工模式向其通信目标传送诸如与等待状态或忙状态相关联的请求的中断请求。 这使得主机设备或从设备在半双工模式下执行的高速数据传输期间处理这样的中断请求。

公开(公告)号：US20100115323A1

公开(公告)日：2010-05-06

申请号：US12593105

申请日：2008-04-10

申请人： Takashi Yamaguchi ,  Tsutomu Sekibe

发明人： Takashi Yamaguchi ,  Tsutomu Sekibe

IPC分类号： G06F1/04 ,  G06F13/14

CPC分类号： G06F1/3203

摘要： A data store system and a data restoration system that can decrease power consumed in data store-processing or data restoration are provided.A data transfer system includes a function block having store data; a storage section for storing the store data transferred from the function block; a bus having a bit width of a predetermined number of bits where the function block and the storage section are connected; and a controller for sending a store period clock to the function block and the storage section at the data store-processing and sending a restoration period clock to the function block and the storage section at the data restoration. In synchronization with the store period clock, the function block sends store data a predetermined number of bits at a time within the bit width of the bus to the bus and the storage section stores the store data sent in sequence from the function block through the bus. In synchronization with the restoration period clock, and the storage section sends the stored store data as many bits as the bit width of the bus at a time to the bus, and the function block reads the store data a predetermined number of bits at a time from the bus.

摘要翻译： 提供了可以减少数据存储处理或数据恢复中消耗的功率的数据存储系统和数据恢复系统。 数据传输系统包括具有存储数据的功能块; 存储部，用于存储从功能块传送的存储数据; 具有功能块和存储部连接的预定位数的位宽的总线; 以及控制器，用于在数据存储处理时向功能块和存储部分发送存储周期时钟，并在数据恢复时向功能块和存储部分发送恢复周期时钟。 与存储周期时钟同步，功能块在总线的位宽度内的一段时间向总线发送预定数量的位的存储数据，并且存储部分存储从功能块通过总线顺序发送的存储数据 。 与恢复周期时钟同步，并且存储部分将存储的存储数据作为总线的位宽度一次发送到总线，并且功能块一次读取存储数据预定的位数 从公共汽车。

公开(公告)号：US20080052534A1

公开(公告)日：2008-02-28

申请号：US11667762

申请日：2005-11-24

申请人： Masaaki Harada ,  Tsutomu Sekibe

发明人： Masaaki Harada ,  Tsutomu Sekibe

IPC分类号： G06F12/14

CPC分类号： G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/105 ,  G06F21/6227 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2137

摘要： A processor (10) manages, in an instruction management unit (103) and a data attribute management unit (105), secure attributes indicating whether instruction code and data stored in an instruction cache (102) and a data cache (104) of the processor (10) are confidential information. When the instruction code and the data are confidential information, the processor (10) also manages secure processing identification information for indicating in which secure process the confidential information is to be used. When the operating mode is switched from the secure mode to the normal mode, only the confidential information is disabled by a memory disabling unit (108). This prevents confidential information from being analyzed by the processor in the normal mode.

摘要翻译： 处理器（10）在指令管理单元（103）和数据属性管理单元（105）中管理指示存储在指令高速缓存（102）和数据高速缓存（104）中的指令代码和数据的安全属性 处理器（10）是机密信息。 当指令代码和数据是机密信息时，处理器（10）还管理安全处理识别信息，用于指示在哪个安全处理中使用机密信息。 当操作模式从安全模式切换到正常模式时，只有秘密信息被存储器禁用单元（108）禁用。 这防止在正常模式下由处理器分析机密信息。

公开(公告)号：US07024532B2

公开(公告)日：2006-04-04

申请号：US10211586

申请日：2002-08-05

申请人： Yoshihiko Takagi ,  Yoshiaki Nakanishi ,  Osamu Sasaki ,  Tsutomu Sekibe

发明人： Yoshihiko Takagi ,  Yoshiaki Nakanishi ,  Osamu Sasaki ,  Tsutomu Sekibe

IPC分类号： G06F12/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3552 ,  G06Q20/35765

摘要： A file management method, whereby inconsistencies can be prevented between a file recorded in a memory card and the file management information that a terminal apparatus manages, without leaking the information of a file made and stored in an in-card processing system. According to this method, a flash memory accessible from two processing systems 100 and 300 is provided. First processing system 100 requests a reservation of an use area of flash memory 200a to second processing system 300, which, upon receiving the request, implements a reservation processing for an area of the memory section and reflects the information of the reserve area upon file management section 230. First processing system 100 performs the processing of writing data into the area reserved by second processing system 300. Inconsistencies between the file management information that a terminal manages and a file actually recorded into the memory section of a secure card can be prevented. Furthermore, exclusive control can be implemented, whereby there will be no direct access from a terminal to the area used for a card-dedicated file recorded therein by means of processing that takes place inside the card.

摘要翻译： 一种文件管理方法，可以防止记录在存储卡中的文件与终端设备管理的文件管理信息之间的不一致性，而不会泄漏在卡内处理系统中制作和存储的文件的信息。 根据该方法，提供从两个处理系统100和300可访问的闪存。 第一处理系统100请求将闪存200a的使用区域预留到第二处理系统300，第二处理系统300在接收到请求时对存储器部分的区域执行预留处理，并将保留区域的信息反映到文件 管理部分230。 第一处理系统100执行将数据写入到由第二处理系统300保留的区域中的处理。 可以防止终端管理的文件管理信息与实际记录在安全卡的存储部分中的文件之间的不一致。 此外，可以实现专用控制，由此通过在卡内部进行的处理，不会从终端直接访问用于其中记录的卡专用文件的区域。

公开(公告)号：US06938144B2

公开(公告)日：2005-08-30

申请号：US10101268

申请日：2002-03-20

申请人： Masayuki Toyama ,  Tsutomu Sekibe

发明人： Masayuki Toyama ,  Tsutomu Sekibe

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/16 ,  G06F12/10

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F2212/2022 ,  G06F2212/7201

摘要： A memory device with a nonvolatile memory and RAM for accessing the nonvolatile memory is generally provided with a table to convert a logical address to a physical address, however, in the invention, the table is divided to a first table on RAM and a second table on the nonvolatile memory. The first table converts specific bits of the logical address to a first physical address indicating a location of the second table. The second table converts the other bits of the logical address to a physical address of a representative page of pages contained in a storage area corresponding to the logical address. A unit operable to access data (a writing unit operable to, a reading unit operable to, and an erasing unit operable to) reaches a target physical address based on the logical address. Such configuration can reduce the capacity of each conversion table.

摘要翻译： 具有用于访问非易失性存储器的非易失性存储器和RAM的存储器件通常设置有用于将逻辑地址转换为物理地址的表，然而，在本发明中，该表被划分为RAM上的第一表和第二表 在非易失性存储器上。 第一表将逻辑地址的特定比特转换成指示第二表的位置的第一物理地址。 第二表将逻辑地址的其他位转换为与逻辑地址对应的存储区域中包含的页面的代表页的物理地址。 可操作以访问数据的单元（可操作的读取单元，可操作的读取单元和可擦除单元）可以基于逻辑地址到达目标物理地址。 这样的配置可以减少每个转换表的容量。

公开(公告)号：US06804742B1

公开(公告)日：2004-10-12

申请号：US09711432

申请日：2000-11-13

申请人： Tomohiko Kitamura ,  Masataka Osaka ,  Tsutomu Sekibe

发明人： Tomohiko Kitamura ,  Masataka Osaka ,  Tsutomu Sekibe

IPC分类号： G06F1336

CPC分类号： G06F11/366 ,  G06F11/364 ,  G06F11/3648

摘要： A system integrated circuit that identifies the cause of a malfunction even if the number of output terminals of a system LSI to be assigned to internal buses in the system LSI is strictly restricted. Comparators 11 to 15 are connected to any of a plurality of buses. Each comparator judges whether a certain expected value matches data transferred on a bus connected to the comparator. The selector unit 10 selects one of the plurality of buses in accordance with the judgement result of the comparator, and outputs data transferred on the selected bus to outside the system integrated circuit so that an observer can observe internal state of the system integrated circuit from outside.

摘要翻译： 即使系统LSI中分配给内部总线的系统LSI的输出端子数量受到严格限制，也能够识别故障原因的系统集成电路。 比较器11至15连接到多个总线中的任一个。 每个比较器判断某个预期值是否匹配与连接到比较器的总线上传输的数据。 选择器单元10根据比较器的判断结果选择多个总线中的一个，并将在所选择的总线上传送的数据输出到系统集成电路外部，使得观察者可以从外部观察系统集成电路的内部状态 。