公开(公告)号：US06804742B1

公开(公告)日：2004-10-12

申请号：US09711432

申请日：2000-11-13

申请人： Tomohiko Kitamura ,  Masataka Osaka ,  Tsutomu Sekibe

发明人： Tomohiko Kitamura ,  Masataka Osaka ,  Tsutomu Sekibe

IPC分类号： G06F1336

CPC分类号： G06F11/366 ,  G06F11/364 ,  G06F11/3648

摘要： A system integrated circuit that identifies the cause of a malfunction even if the number of output terminals of a system LSI to be assigned to internal buses in the system LSI is strictly restricted. Comparators 11 to 15 are connected to any of a plurality of buses. Each comparator judges whether a certain expected value matches data transferred on a bus connected to the comparator. The selector unit 10 selects one of the plurality of buses in accordance with the judgement result of the comparator, and outputs data transferred on the selected bus to outside the system integrated circuit so that an observer can observe internal state of the system integrated circuit from outside.

摘要翻译： 即使系统LSI中分配给内部总线的系统LSI的输出端子数量受到严格限制，也能够识别故障原因的系统集成电路。 比较器11至15连接到多个总线中的任一个。 每个比较器判断某个预期值是否匹配与连接到比较器的总线上传输的数据。 选择器单元10根据比较器的判断结果选择多个总线中的一个，并将在所选择的总线上传送的数据输出到系统集成电路外部，使得观察者可以从外部观察系统集成电路的内部状态 。

公开(公告)号：US06842104B1

公开(公告)日：2005-01-11

申请号：US09526154

申请日：2000-03-15

申请人： Masataka Osaka ,  Tsutomu Sekibe

发明人： Masataka Osaka ,  Tsutomu Sekibe

IPC分类号： G06F13/00 ,  G06F13/40 ,  H03K17/00

CPC分类号： G06F13/4022 ,  G06F13/4031

摘要： A cross-bus switch apparatus which establishes simultaneously two or more pairs of connections between (i) a source bus arbitrarily selected from a plurality of source buses connected to one or more source apparatuses and (ii) a destination bus arbitrarily selected from a plurality of destination buses connected to one or more destination apparatuses. The cross-bus switch apparatus includes: a plurality of cross-bus switch units. The plurality of source buses are grouped into a plurality of source bus groups which are each connected to one of the plurality of cross-bus switch units. The plurality of destination buses are grouped into a plurality of destination bus groups which are each connected to one of the plurality of cross-bus switch units. Each cross-bus switch unit is connected to either (i) a source bus group or a destination bus group, or (ii) a source bus group and a destination bus group.

摘要翻译： 一种交叉总线开关装置，其在（i）从连接到一个或多个源装置的多个源总线任意选择的源总线和（ii）从多个源装置中任意选择的目的地总线之间同时建立两对或更多对连接 连接到一个或多个目的地设备的目的地总线。 交叉总线开关装置包括：多个交叉总线开关单元。 多个源总线被分组成多个源总线组，每个源总线组各自连接到多个交叉总线开关单元中的一个。 多个目的地总线被分组为多个目的地总线组，其各自连接到多个交叉总线开关单元中的一个。 每个交叉总线开关单元连接到（i）源总线组或目的地总线组，或者（ii）源总线组和目的地总线组。

公开(公告)号：US07210017B2

公开(公告)日：2007-04-24

申请号：US10818166

申请日：2004-04-05

申请人： Masataka Osaka

发明人： Masataka Osaka

IPC分类号： G06F12/00

CPC分类号： G06F13/1689

摘要： A memory control unit and a memory unit is connected to each other by a bus used for transfer of address, data and control signals. The memory control unit outputs a first command including a first predetermined location in the memory unit, to the memory unit. The memory control unit outputs a second command including a second predetermined location in the memory unit, to the memory unit when a predetermined time period has elapsed since the output of the first command.

摘要翻译： 存储器控制单元和存储单元通过用于传送地址，数据和控制信号的总线相互连接。 存储器控制单元将包括存储器单元中的第一预定位置的第一命令输出到存储器单元。 当从第一命令的输出起经过预定​​时间段时，存储器控制单元将包括存储器单元中的第二预定位置的第二命令输出到存储器单元。

公开(公告)号：US5594887A

公开(公告)日：1997-01-14

申请号：US332759

申请日：1994-11-01

申请人： Masataka Osaka

发明人： Masataka Osaka

IPC分类号： G06F12/08

CPC分类号： G06F12/0826 ,  G06F12/0831 ,  G06F2212/622

摘要： In a system bus connected to at least one CPU having a cache memory used for increasing memory access speed in an engineering workstation or the like, a main memory controller including a status memory for storing owned and unowned statuses in a main memory and a cache memory of data associated with an access operation to a system bus connected to at least one CPU having a cache memory performed by an access means of a CPU or the like, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before the time for outputting a data invalidating signal from the cache memory elapses in the case of the owned status and for reading the data in the cache memory after the data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring accesses to the system bus and for rewriting the status in the status memory according to the result of the monitoring.

摘要翻译： 在连接到具有用于在工程工作站等中增加存储器访问速度的高速缓冲存储器的至少一个CPU的系统总线中，主存储器控制器包括用于在主存储器和高速缓冲存储器中存储拥有和不知情状态的状态存储器 与连接到具有由CPU等的访问装置执行的高速缓冲存储器的至少一个CPU的系统总线的访问操作相关联的数据的存储器控​​制部分，响应于指示存储状态的信号以读取 在拥有状态的情况下经过用于输出来自高速缓冲存储器的数据无效信号的时间之前的主存储器中的数据，并且在未知状态的情况下输出数据无效信号之后读取高速缓冲存储器中的数据， 以及状态重写控制部分，用于监视对系统总线的访问，并根据监视结果重写状态存储器中的状态。

公开(公告)号：US06424380B1

公开(公告)日：2002-07-23

申请号：US09104734

申请日：1998-06-25

申请人： Masataka Osaka

发明人： Masataka Osaka

IPC分类号： H04N544

CPC分类号： H04N21/435 ,  H04N1/00098 ,  H04N5/4401 ,  H04N5/445 ,  H04N5/44543 ,  H04N5/45 ,  H04N21/235 ,  H04N21/42692 ,  H04N21/4341 ,  H04N21/8153

摘要： A digital broadcast receiving apparatus, for receiving a plurality of pieces of compressed still image data repeatedly transmitted from a digital broadcast transmitting apparatus and for outputting a still image selected by a user as a TV signal, fetches still image data into a main memory prior to a selecting operation made by the user, expands still image data of a still image selected by the user using an AV decoder of an MPEG decoder, and outputs an image signal of the selected still image according to the expanded still image data.

摘要翻译： 一种数字广播接收装置，用于接收从数字广播发送装置重复发送的多个压缩静止图像数据，并将由用户选择的静止图像输出为TV信号，将静止图像数据在 由用户进行的选择操作使用MPEG解码器的AV解码器来扩展由用户选择的静止图像的静止图像数据，并且根据扩展的静止图像数据输出所选择的静止图像的图像信号。

公开(公告)号：US20100090718A1

公开(公告)日：2010-04-15

申请号：US12598011

申请日：2008-06-09

申请人： Atsushi Ubukata ,  Ryuta Tsutsui ,  Masataka Osaka ,  Yoshiteru Mino ,  Tomohisa Sezaki ,  HIrotaka Doi

发明人： Atsushi Ubukata ,  Ryuta Tsutsui ,  Masataka Osaka ,  Yoshiteru Mino ,  Tomohisa Sezaki ,  HIrotaka Doi

IPC分类号： G01R31/26

CPC分类号： G01R31/3177 ,  G01R31/3187

摘要： States of LSI internal signals (100 to 107) are monitored. Signal name information (31), signal state information (32), and information (33) about time in an LSI when a signal undergoes a state transition, are packetized and output as trace information (10) to the outside. In a development supporting device, the trace information (10) is decoded, the time information of the LSI is converted into real-time information, and based on the resultant information, a waveform of an LSI internal signal is reproduced. A plurality of LSI internal signals can be traced using terminals (16) the number of which is smaller than the number of the signals to be traced.

摘要翻译： 监视LSI内部信号状态（100〜107）。 将信号状态信息（31），信号状态信息（32）以及关于信号进行状态转换时的LSI的时间的信息（33）分组化并作为跟踪信息（10）输出到外部。 在显影支持装置中，跟踪信息（10）被解码，LSI的时间信息被转换为实时信息，并且基于所得到的信息，再现LSI内部信号的波形。 可以使用其数量小于要跟踪的信号的数量的终端（16）来跟踪多个LSI内部信号。

公开(公告)号：US20090094408A1

公开(公告)日：2009-04-09

申请号：US11995892

申请日：2005-12-15

申请人： Masataka Osaka

发明人： Masataka Osaka

IPC分类号： G06F12/02 ,  G06F15/177

CPC分类号： G06F8/654

摘要： After power-on, the start-up of a CPU 112 is suppressed by a microcomputer start-up suppressing/DMA start-up controlling device 101. Before the start-up of the CPU 112, a program read by a memory card I/F 103 is written in a writable ROM 105 by a DMA controlling device 102. After the start-up of the CPU 112, the CPU 112 executes the program written in the writable ROM 105.

摘要翻译： 上电后，通过微型计算机启动抑制/ DMA启动控制装置101来抑制CPU 112的启动。在CPU 112启动之前，由存储卡I / F103由DMA控制装置102写入可写ROM105中。在CPU 112启动之后，CPU 112执行写在可写ROM105中的程序。

公开(公告)号：US06820152B2

公开(公告)日：2004-11-16

申请号：US10120327

申请日：2002-04-10

申请人： Hideyuki Kanzaki ,  Masataka Osaka

发明人： Hideyuki Kanzaki ,  Masataka Osaka

IPC分类号： G06F1338

CPC分类号： G06F13/161

摘要： A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI 100 writes into the transfer rate information storage unit 111 the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit 112 determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit 114 grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.

摘要翻译： 一种用于在总线主机之间仲裁存储器访问争用的存储器控​​制装置，同时确保关于每个总线主机在所需时间范围内所需的传送速率。 LSI100外部的装置向传送速率信息存储部111写入表示传送速度的传送速度信息和要确保传送速率的时间段。 作为响应，定时信息生成单元112将最短时间段确定为周期，并且还针对每个总线主机确定基于作为总线使用许可时间段的存储器总线带宽来确保所需传送速率所需的时间。 仲裁器单元114将总线使用权随时间顺序地授予每个总线主控器发出相应的总线使用许可时间段的总线请求。