公开(公告)号：US20240422352A1

公开(公告)日：2024-12-19

申请号：US18816474

申请日：2024-08-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC: H04N19/593 ,  H04N19/176 ,  H04N19/44

Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: prohibits a first splitting method when arrangement and shapes of blocks obtained by splitting a first block multiple times by the first splitting method are identical to arrangement and shapes of blocks obtained by splitting the first block multiple times by a second splitting method different from the first splitting method, and when scan order of the blocks obtained by the first splitting method is identical to scan order of the blocks obtained by the second splitting method; and encodes the first block.

公开(公告)号：US20240388707A1

公开(公告)日：2024-11-21

申请号：US18787763

申请日：2024-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.

公开(公告)号：US20240380920A1

公开(公告)日：2024-11-14

申请号：US18779644

申请日：2024-07-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/52 ,  H04N19/137 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.

公开(公告)号：US20240380918A1

公开(公告)日：2024-11-14

申请号：US18779477

申请日：2024-07-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/52 ,  H04N19/137 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.

公开(公告)号：US20240380917A1

公开(公告)日：2024-11-14

申请号：US18779432

申请日：2024-07-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/52 ,  H04N19/137 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.

公开(公告)号：US20240357171A1

公开(公告)日：2024-10-24

申请号：US18763032

申请日：2024-07-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Toshiyasu SUGIO ,  Noritaka IGUCHI ,  Takahiro NISHI ,  Zheng WU ,  Keng Liang LOI ,  Chung Dean HAN

IPC: H04N19/597 ,  H04N19/13 ,  H04N19/96

CPC classification number: H04N19/597 ,  H04N19/13 ,  H04N19/96

Abstract: A three-dimensional data decoding method includes: obtaining a bitstream including encoded three-dimensional points generated by encoding three-dimensional points each of which is represented by a first angle, a second angle, and a distance; determining a reference three-dimensional point among the three-dimensional points; and performing, according to the first angle of the reference three-dimensional point, at least one of arithmetic decoding or debinarizing on encoded information of a current encoded three-dimensional point included in the encoded three-dimensional points to generate information of a current three-dimensional point included in the three-dimensional points, the information excluding the first angle.

公开(公告)号：US20240348775A1

公开(公告)日：2024-10-17

申请号：US18756664

申请日：2024-06-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US20240292032A1

公开(公告)日：2024-08-29

申请号：US18659567

申请日：2024-05-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke KATO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/61 ,  H04N19/103 ,  H04N19/13 ,  H04N19/136 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91

CPC classification number: H04N19/61 ,  H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91 ,  H04N19/103 ,  H04N19/136

Abstract: An encoder includes circuitry and memory. In both of a first type of residual coding where an orthogonal transform is applied to a current block and a second type of residual coding where the orthogonal transform is skipped, wherein when a number of CABAC processes is within an allowable range, the circuitry encodes coefficient information flags by CABAC, each of the coefficient information flags relating to a coefficient included in the current block; and otherwise, the circuitry skips the encoding of the coefficient information flags; and the circuitry encodes a remainder value of the coefficient with Golomb-Rice code when the coefficient information flags are encoded; and the circuitry encodes a value of the coefficient with the Golomb-Rice code when the plurality of coefficient information flags are not encoded, wherein the coefficient information flags are partially different between the first type of residual coding and the second type of residual coding.

公开(公告)号：US20240236341A1

公开(公告)日：2024-07-11

申请号：US18611971

申请日：2024-03-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/196 ,  H04N19/105 ,  H04N19/14 ,  H04N19/176 ,  H04N19/436

CPC classification number: H04N19/196 ,  H04N19/105 ,  H04N19/14 ,  H04N19/176 ,  H04N19/436

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives a correction parameter using only a neighboring reconstructed image that neighbors a processing unit which has a determined size and is located at an upper left of a current block to be processed in an image, among neighboring reconstructed images that neighbor the current block, and performs correction processing of the current block based on the correction parameter derived, when the current block has a size larger than the determined size.

公开(公告)号：US20240187617A1

公开(公告)日：2024-06-06

申请号：US18440292

申请日：2024-02-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/31

CPC classification number: H04N19/31

Abstract: An encoder includes circuitry, and memory coupled to the circuitry. The circuitry, in operation, for each of a plurality of sub-bitstreams having mutually different frame rates, encodes identification information into a header of a bitstream including the plurality of sub-bitstreams, the identification information indicating a temporal ID that is an identifier of a temporal layer related to a temporal scalability and corresponds to the sub-bitstream, and encodes level information indicating a conformance level of the sub-bitstream.