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公开(公告)号：US20140269131A1
公开(公告)日：2014-09-18
申请号：US13826427
申请日：2013-03-14
IPC分类号： G11C7/08
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译： 存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。 每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。 多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号， 相应的多个读出放大器之一。
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公开(公告)号：US06608789B2
公开(公告)日：2003-08-19
申请号：US10027547
申请日：2001-12-21
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.
摘要翻译： 读出放大器（40）使用主体短路装置（60）来选择性地使作为差分感测对的两个晶体管（44,48）的主体电短路。 注入到体内的电荷的均衡起到使两个物体之间的失调电压最小化的作用。 身体短路装置在感测操作之后并且在确定预充电信号以启动感测放大器的输出的预充电之后，响应于身体控制信号选择性地短路身体。
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公开(公告)号：US20130290753A1
公开(公告)日：2013-10-31
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译： 根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。 根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。 使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。 提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。
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公开(公告)号：US07164293B2
公开(公告)日：2007-01-16
申请号：US10902204
申请日：2004-07-29
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A circuit (50) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit (50) functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit (54) latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).
摘要翻译： 接收动态信号的电路（50）执行逻辑和锁存以实现高速操作。 电路具有定义评估阶段和预充电阶段的时钟，其中动态信号在评估阶段被评估。 电路（50）通过在评估阶段期间对锁存节点（INT）进行预充电来起作用，然后在评估阶段期间执行评估。 评估导致向锁存节点提供有效的逻辑状态。 锁存电路（54）在预充电阶段期间锁存该有效状态，并且在预充电阶段将其保持在该有效状态。 这可以适于选择哪个动态信号被耦合并锁存在锁存节点（INT）上。
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公开(公告)号：US5367494A
公开(公告)日：1994-11-22
申请号：US113632
申请日：1993-08-31
CPC分类号： G11C8/12 , G11C11/005 , G11C7/1042
摘要： A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.
摘要翻译： 存储器装置（28）同时执行两个或多个存储位置的存储器存取操作。 存储器件（28）由多个存储体解码逻辑电路（30,32,56）和多个存储器组（34,52）组成。 每个解码逻辑电路解码设置的第一信息和控制信号，以使第一存储体开始并完成存储器访问操作。 每个存储体由多个锁存电路（39,40,42,50）组成，以存储执行存储器访问操作所必需的预定信息和控制信号。 因此，第二控制信号和信息集可以使存储器装置（28）内的第二存储器组能够在第一存储器存取操作的同时执行第二存储器存取操作。
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公开(公告)号：US4899317A
公开(公告)日：1990-02-06
申请号：US151044
申请日：1988-02-01
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： In a static random access memory in which the array is comprised of MOS transistors and at least some of the peripheral circuits are comprised of bipolar transistors, the bit lines and data lines are precharged to a base to emitter voltage drop (i.e. one Vbe) below the positive power supply voltage. This increases cell stability. Additionally, Vbe varies comparatively little over process. Additionally, precharging the bit lines and data lines to a Vbe below the positive power supply voltage allows for the use of a high speed bipolar differential amplifier in its optimum operating range as the first stage sense amplifier.
摘要翻译： 在其中阵列由MOS晶体管组成的静态随机存取存储器中，并且至少一些外围电路由双极型晶体管组成，位线和数据线被预充电到低于基极到发射极的电压降（即一个Vbe） 正电源电压。 这增加了细胞稳定性。 此外，Vbe在过程中变化相对较小。 此外，将位线和数据线预充电到低于正电源电压的Vbe允许在其最佳工作范围内使用高速双极差分放大器作为第一级感测放大器。
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公开(公告)号：US09317087B2
公开(公告)日：2016-04-19
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译： 根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。 根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。 使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。 提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。
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公开(公告)号：US09225337B2
公开(公告)日：2015-12-29
申请号：US14191684
申请日：2014-02-27
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译： 一种用于确定相对于阈值温度的温度阈值指示的电路。 电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。 在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。 响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。
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公开(公告)号：US09117498B2
公开(公告)日：2015-08-25
申请号：US13826427
申请日：2013-03-14
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译： 存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。 每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。 多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号， 相应的多个读出放大器之一。
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公开(公告)号：US06928005B2
公开(公告)日：2005-08-09
申请号：US10703657
申请日：2003-11-05
CPC分类号： G11C15/00
摘要： A memory including a NOR logic gate having an input coupled to a bitline (BL) and an input to receive the complement of the data value (DATABAR). The memory also including a NOR logic gate having an input coupled to the bitline bar (BLBAR) and an input to receive the data value (DATA). A combine stage is also included having an input coupled to an output of the NOR logic gate, an input coupled to an output of the NOR logic gate, and an output to provide a miss indicator (MISS). The miss indicator (MISS) indicates when a value on the bitline (BL) does not match the data value (DATA). The memory also comprising a plurality of bitcells coupled to the bitline (BL) and bitline bar (BLBAR), where each of the plurality of bitcells is coupled to a corresponding word line.
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