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11.发明授权System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置公开(公告)号：US07412546B2
公开(公告)日：2008-08-12
申请号：US11320277
申请日：2005-12-27
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。
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12.发明授权System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置公开(公告)号：US07200696B2
公开(公告)日：2007-04-03
申请号：US09828342
申请日：2001-04-06
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit feature is communicated to the network processor to indicate whether the transmission of a particular frame is ended and a new frame is to be transmitted.
摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括多个控制块，一个用于每个数据缓冲器，每个控制块包含用于将一个缓冲器链接到另一缓冲器以进行传输的控制信息。 每个控制块具有作为单个位的最后位特征，并且指示何时发送具有最后位的数据缓冲器。 这最后一位功能是一个可以设置为零或一个的位。 当附加数据缓冲器被链接到先前的数据缓冲器指示要发送附加数据缓冲器时，最后一位特征处于第一位置，而当没有附加数据缓冲器被链接到先前的数据缓冲器时，第二位置 。 将最后一位特征的位置传送给网络处理器，以指示特定帧的传输是否结束，并且要发送新的帧。
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公开(公告)号：US06987760B2
公开(公告)日：2006-01-17
申请号：US09838395
申请日：2001-04-19
申请人： Jean Louis Calvignac , William John Goetzinger , Glen Howard Handlogten , Marco C. Heddes , Joseph Franklin Logan , James Francis Mikos , David Alan Norgaard , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , William John Goetzinger , Glen Howard Handlogten , Marco C. Heddes , Joseph Franklin Logan , James Francis Mikos , David Alan Norgaard , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：US06681340B2
公开(公告)日：2004-01-20
申请号：US09792533
申请日：2001-02-23
IPC分类号： G06F1110
CPC分类号： H04L1/0043 , H04L1/0063
摘要： A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.
摘要翻译： 一种用于有效实施纠错码方案的方法和系统。 在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。 数据帧可以与帧控制块相关联。 处理器包括被配置为存储与一个或多个数据帧相关联的一个或多个帧控制块的第一队列。 处理器还包括被配置为存储与数据帧不相关联的一个或多个帧控制块的第二队列。 与第一队列中的一个或多个数据帧相关联的一个或多个帧控制块包括用于存储奇偶校验位的位。 第二队列中的一个或多个帧控制块包括用于存储纠错码方案的代码的多个比特。
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公开(公告)号：US06658546B2
公开(公告)日：2003-12-02
申请号：US09792557
申请日：2001-02-23
IPC分类号： G06F1200
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9047
摘要： A method and system for reserving frame modification information in a data storage unit. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data. The processor may further comprise a data storage unit coupled to the data flow unit where the data storage unit comprises a plurality of buffers. The plurality of buffers is configured to store frames of data. A first buffer may be accessed to store the ending frame data of a first frame. A first bank in the first buffer stores the end of the first frame. A second bank in a second buffer may be reserved for storing frame modification information where the second bank corresponds to the first bank in the first buffer that stores the end of the first frame.
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16.发明授权Systems and methods for implementing counters in a network processor with cost effective memory 失效在具有成本效益的存储器的网络处理器中实现计数器的系统和方法公开(公告)号：US07293158B2
公开(公告)日：2007-11-06
申请号：US11070060
申请日：2005-03-02
CPC分类号： H04L49/901 , H04L49/90
摘要： Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.
摘要翻译： 公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。 实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。 网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。 实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。 每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器递增从存储器接收的计数器值。 在R-M-W周期的写周期期间，递增的值被写入存储器。 写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。
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公开(公告)号：US06910092B2
公开(公告)日：2005-06-21
申请号：US10016800
申请日：2001-12-10
申请人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
发明人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
CPC分类号： G06F13/4265
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.
摘要翻译： 网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。 可选的调度器芯片耦合到数据流芯片。 命名的组件被复制以创建对称的入口和出口结构。 芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。
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18.发明授权公开(公告)号：US07149212B2
公开(公告)日：2006-12-12
申请号：US10095844
申请日：2002-03-12
IPC分类号： H04L12/50
CPC分类号： H04L49/9063 , H04L29/06 , H04L49/90 , H04L49/901 , H04L69/12 , H04L69/22
摘要： An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.
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19.发明授权公开(公告)号：US07085266B2
公开(公告)日：2006-08-01
申请号：US10095792
申请日：2002-03-12
IPC分类号： H04L12/50
CPC分类号： G06F15/7825
摘要： An interface to interconnect chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The chips can be configured in different operational modes which dictates what portion of a frame is to be transmitted between selected chips of the system.
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20.发明授权Implementing pointer and stake model for frame alteration code in a network processor 失效在网络处理器中实现帧更改代码的指针和投注模型公开(公告)号：US08170024B2
公开(公告)日：2012-05-01
申请号：US11934810
申请日：2007-11-05
申请人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
发明人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。 为选择用于发送的分组提供当前指针和分支。 保持当前指针用于跟踪分组中帧更改操作的当前位置。 保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。 当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。 指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。 高级指针指令允许当前和指针指针以任意数量的字节进入数据包。
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