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公开(公告)号：US08566059B2
公开(公告)日：2013-10-22
申请号：US12633151
申请日：2009-12-08
申请人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
CPC分类号： G06F17/5022 , G06F11/261 , G06F2217/70
摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
摘要翻译： 一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则 满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。
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12.发明申请Automated Termination of Selected Software Applications in Response to System Events 失效自动终止所选软件应用程序以响应系统事件公开(公告)号：US20100211950A1
公开(公告)日：2010-08-19
申请号：US12389163
申请日：2009-02-19
IPC分类号： G06F9/46
摘要： The illustrative embodiments disclose a computer implemented method, apparatus, and computer program product for managing a set of applications. In one embodiment, the process registers a system management event in an application configuration database. Responsive to detecting the registered system management event during execution of one application of the set of applications, the process identifies applications of the set of applications associated with the registered system management event that are executing. The process then terminates the applications of the set of applications associated with the registered system management event that are executing. Responsive to terminating the applications of the set of applications associated with the registered system managing event that are executing, the process then executes a handler that processes the registered system management event.
摘要翻译： 说明性实施例公开了一种用于管理一组应用的计算机实现的方法，装置和计算机程序产品。 在一个实施例中，该过程在应用配置数据库中注册系统管理事件。 响应于在执行一组应用程序的一个应用程序期间检测注册的系统管理事件，该过程识别与正在执行的注册的系统管理事件相关联的应用程序的应用程序。 然后，该过程终止与正在执行的注册的系统管理事件相关联的一组应用的应用。 响应于终止与正在执行的注册系统管理事件相关联的一组应用的应用，该过程然后执行处理注册的系统管理事件的处理程序。
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公开(公告)号：US20080172576A1
公开(公告)日：2008-07-17
申请号：US11622055
申请日：2007-01-11
申请人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
发明人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
IPC分类号： G06F11/26
CPC分类号： G06F11/261
摘要： A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.
摘要翻译： 适用于VLSI设计的诊断过程，以解决诊断解决的准确性。 基于环境的故障数据驱动自适应测试方法，其中测试模式集合和数据收集失败，以便成功诊断分辨率。 基于环境的故障数据用于诊断仿真，以实现更准确的基于环境的故障标注。 当需要时，该过程中将包含其他信息，以进一步完善和定义模拟或标注结果。 类似地，根据需要采用自适应测试模式生成方法来提高诊断分辨率。
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14.发明授权Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis 失效降低半导体芯片红外成像曝光时间的技术进行故障分析公开(公告)号：US06442720B1
公开(公告)日：2002-08-27
申请号：US09326226
申请日：1999-06-04
IPC分类号： G01R3128
CPC分类号： G01R31/31858
摘要： The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, and observing an exercised failing circuit. The invention can include the use of PICA techniques to observe the exercised failing circuit. In another embodiment, the invention can include using LBIST or a WRP technique to search for the failing pattern. In yet another it includes the step of using an algorithm to exercise the exercised failing circuit. In another embodiment, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern. The algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern. In one embodiment, one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict. In another embodiment the method further includes the step of using an algorithm to densify the pattern set.
摘要翻译： 本发明可以包括用于测试IC芯片的方法和系统，包括以下步骤：对第一故障模式执行二进制搜索，确定故障接收器锁存器，执行后锥迹线以确定所有源锁存器，确定源锁存器逻辑状态 将源锁存器逻辑状态定位在扫描链中，通过在没有系统L1时钟的情况下在源锁存器上施加逻辑转换并观察行使的故障电路来执行芯片扫描路径。 本发明可以包括使用PICA技术来观察行使的故障电路。 在另一个实施例中，本发明可以包括使用LBIST或WRP技术来搜索失败的模式。 在另一方面，它包括使用算法来锻炼锻炼的故障电路的步骤。 在另一个实施例中，该方法包括创建要被扫描的网络图案的步骤，包括导致执行故障电路的原始图案的和以及原始图案的一个或多个偏移版本。 该算法可以包括一个步骤，其中移位版本中的一个被移位了多个时钟，其中时钟数等于原始图案的长度。 在一个实施例中，移位版本中的一个被移位了多个时钟，其中选择时钟的数量，使得原始模式和移位版本之一的总和不会引起扫描冲突。 在另一个实施例中，该方法还包括使用算法来密集模式集的步骤。
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15.发明授权Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips 失效分区伪随机逻辑测试，以提高半导体芯片的可制造性公开(公告)号：US06314540B1
公开(公告)日：2001-11-06
申请号：US09290516
申请日：1999-04-12
IPC分类号： G01R3128
CPC分类号： G01R31/31813 , G01R31/318385
摘要： A partitioned pseudo-random logic test (PRLT) for integrated circuit chips for improving manufacturability is disclosed. The technique makes available previously difficult-to-collect empirical data to accurately improve test effectiveness while significantly lowering test time and test cost. An embodiment includes a method for testing IC chips, including generating values for latches for a complete test pattern set, partitioning the test pattern set into a plurality of partitioned test pattern subsets, and running the subsets against a chip. Another embodiment is directed to a system that tests IC chips, having a latch value generator that generates values for latches for a complete test pattern set, a test pattern divider that partitions the complete test pattern set into a plurality of partitioned test pattern subsets, and a tester that runs the partitioned test pattern subsets against the chip.
摘要翻译： 公开了一种用于提高可制造性的集成电路芯片的分区伪随机逻辑测试（PRLT）。 该技术使以前难以收集的经验数据可以准确地提高测试效果，同时显着降低测试时间和测试成本。 一个实施例包括一种用于测试IC芯片的方法，包括产生用于完整测试模式集合的锁存器的值，将测试模式集划分成多个分割测试模式子集，以及针对芯片运行子集。另一个实施例涉及 测试IC芯片的系统，具有为整个测试模式集合产生锁存器的值的锁存值产生器，将完整测试模式集分成多个分区测试模式子集的测试模式分割器，以及运行分区的测试器 针对芯片的测试模式子集。
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公开(公告)号：US20110137602A1
公开(公告)日：2011-06-09
申请号：US12633151
申请日：2009-12-08
申请人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
CPC分类号： G06F17/5022 , G06F11/261 , G06F2217/70
摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
摘要翻译： 一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则 满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。
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公开(公告)号：US07831863B2
公开(公告)日：2010-11-09
申请号：US11622055
申请日：2007-01-11
申请人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
发明人： Mary P. Kusko , Gary W. Maier , Franco Motika , Phong T. Tran
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.
摘要翻译： 适用于VLSI设计的诊断过程，以解决诊断解决的准确性。 基于环境的故障数据驱动自适应测试方法，其中测试模式集合和数据收集失败，以便成功诊断分辨率。 基于环境的故障数据用于诊断仿真，以实现更准确的基于环境的故障标注。 当需要时，该过程中将包含其他信息，以进一步完善和定义模拟或标注结果。 类似地，根据需要采用自适应测试模式生成方法来提高诊断分辨率。
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公开(公告)号：US20100146019A1
公开(公告)日：2010-06-10
申请号：US12329797
申请日：2008-12-08
CPC分类号： G06F17/30067 , G06F17/30147
摘要： A computer-implemented method, system and computer program product for managing computer file storage is presented. In one embodiment the method includes receiving a file for storage. In response to determining that the file exceeds a pre-determined size, the file is stored in a pre-designated folder that is reserved for oversized files.
摘要翻译： 提出了一种用于管理计算机文件存储的计算机实现的方法，系统和计算机程序产品。 在一个实施例中，该方法包括接收用于存储的文件。 响应于确定文件超过预定大小，该文件被存储在为超大文件保留的预先指定的文件夹中。
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19.发明申请ITERATIVE TEST GENERATION AND DIAGNOSTIC METHOD BASED ON MODELED AND UNMODELED FAULTS 审中-公开基于建模和未修正故障的迭代测试和诊断方法公开(公告)号：US20080115029A1
公开(公告)日：2008-05-15
申请号：US11552567
申请日：2006-10-25
CPC分类号： G01R31/318364 , G01R31/318342 , G06F11/261
摘要： A diagnostic and characterization tool applicable to structural VLSI designs to address problems associated with fault tester interactive pattern generation and ways of effectively reducing diagnostic test time while achieving greater fail resolution. Empirical fail data drives the creation of adaptive test patterns which localize the fail to a precise location. This process iterates until the necessary localization is achieved. Both fail signatures and associated callouts as well as fail signatures and adaptive patterns are stored in a library to speed diagnostic resolution. The parallel tester application and adaptive test generation provide an efficient use of resources while reducing overall test and diagnostic time.
摘要翻译： 一种诊断和表征工具，适用于结构化VLSI设计，以解决与故障测试者交互式模式生成相关的问题，以及有效降低诊断测试时间并实现更高故障分辨率的方法。 经验失效数据驱动创建自适应测试模式，将故障定位到精确位置。 该过程重复直到实现必要的定位。 故障签名和关联的标注以及故障签名和自适应模式都存储在库中以加快诊断分辨率。 并行测试仪应用和自适应测试生成提供了有效利用资源，同时降低了整体测试和诊断时间。
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20.发明授权Method and apparatus for facilitating random pattern testing of logic structures 失效用于促进逻辑结构的随机模式测试的方法和装置公开(公告)号：US06836865B2
公开(公告)日：2004-12-28
申请号：US09973398
申请日：2001-10-09
IPC分类号： G01R3128
CPC分类号： G01R31/318385 , G01R31/31813 , G01R31/318544
摘要： A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.
摘要翻译： 公开了一种用于准备用于随机模式测试的逻辑结构的方法。 在本发明的示例性实施例中，该方法包括配置数据扫描链内的选择机制，所述选择机制配置在数据扫描链中的第一寄存器和第二寄存器之间。 平行数据路径在扫描链内路由，并行数据路径从第一寄存器的输入侧开始，通过选择机制运行，并在第二寄存器的输入端结束。 如此配置，选择机制能够将来自正常数据路径的输入数据的源路径切换到所述第二寄存器到并行数据路径。 当选择并行数据路径作为第二寄存器的输入数据的源路径时，加载到第二寄存器中的数据匹配加载到第一寄存器中的数据。
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