公开(公告)号：US09640250B1

公开(公告)日：2017-05-02

申请号：US15155076

申请日：2016-05-16

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Stephen Edward Liles ,  Brian Joy Reed

IPC: G11C15/00 ,  G11C11/419 ,  G11C15/04

CPC classification number: G06F12/0895 ,  G11C7/1006 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored in a data row of the memory array to generate true and complement sense amplifier inputs. The true and complement sense amplifier inputs are amplified in the sense amplifier to generate a single-ended match signal. The single-ended match signal can be aggregated with other single-ended match signals in the data row to determine whether there is a hit or miss for a compare operation on the entire data row.

公开(公告)号：US20170052900A1

公开(公告)日：2017-02-23

申请号：US15087077

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Milind Ram Kulkarni ,  Benjamin John Bowers

IPC: G06F12/10 ,  G06F1/06

CPC classification number: G06F12/10 ,  G06F1/06 ,  G06F12/0879 ,  G06F12/0895 ,  G06F12/1027 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/65

Abstract: Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.

Abstract translation: 公开了在索引的地址空间内高效地生成用于行选择的选择掩码。 在这方面，在一个方面，提供了一种索引阵列电路，包括指示行选择的开始索引的数组行的开始指示符和指示行选择的结束索引的数组行的结束指示符。 索引阵列电路还包括以逻辑序列排序的多个索引阵列行，每个包括行级比较电路。 每个行级比较电路被配置为基于索引数组行的逻辑地址的位的子集与开始指示符的相应的子集的第一并行比较来生成选择掩码指示符，以及子集的第二并行比较 的索引数组行的逻辑地址的位与终端指示符的相应的子集。

公开(公告)号：US20140223093A1

公开(公告)日：2014-08-07

申请号：US13798767

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： David Paul Hoff ,  Tracey A. Della Rova ,  Jason P. Martzloff

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G06F7/74 ,  G11C15/043 ,  H03K19/0013

Abstract: The hybrid dynamic-static encoder described herein may combine dynamic and static structural and logical design features that strategically partition dynamic nets and logic to substantially eliminate redundancy and thereby provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder may include identical top and bottom halves, which may be combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half may use a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith may be evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder may have a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.

Abstract translation: 本文描述的混合动态静态编码器可以组合动态和静态结构和逻辑设计特征，其策略性地分割动态网络和逻辑以基本上消除冗余，从而相对于具有等效逻辑延迟的全动态编码器提供面积，功率和泄漏节省 。 例如，混合动态静态编码器可以包括相同的顶部和底部两半，其可以被组合以产生最终编码索引，命中和多命中输出。 每个编码器一半可以为每个索引位使用动态网络，其中匹配搜索关键点的行。 如果已经点划线以指示该行与搜索关键字匹配，则可以评估与之相关联的动态网络以反映与该行相关联的索引。 因此，混合动态静态编码器可以具有减小的较小动态网络集合，其利用索引，命中和多命中动态网络上的冗余下拉结构。