公开(公告)号：US09665489B2

公开(公告)日：2017-05-30

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

公开(公告)号：US20160232091A1

公开(公告)日：2016-08-11

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

Abstract translation: 方面包括用于实现选择可用的共享高速缓冲存储器作为受害者高速缓存的计算设备，系统和方法。 计算设备可以使用可用的共享高速缓冲存储器空间来识别远程共享高速缓冲存储器，以用作受害者高速缓存。 为了选择适当的可用共享高速缓冲存储器，计算设备可以检索与所标识的远程共享高速缓冲存储器相关联的识别的远程共享高速缓冲存储器的数据或与所标识的远程共享高速缓冲存储器有关的诸如性能速度， 尺寸。 使用所检索的数据，计算设备可以确定所识别的远程共享高速缓冲存储器以用作受害者高速缓存，并选择确定的远程共享高速缓冲存储器以用作受害者高速缓存。

公开(公告)号：US09747209B1

公开(公告)日：2017-08-29

申请号：US15054295

申请日：2016-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： Feng Wang ,  Bohuslav Rychlik

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0868

CPC classification number: G06F12/0811 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/313

Abstract: Various embodiments of methods and systems for cache-level memory management in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through application of customized hashing algorithms at the lower level cache of individual application clients. Advantageously, for those application clients that do not require or benefit from hashing transaction traffic their transactions are not subjected to hashing. For those application clients that do benefit from hashing transaction traffic in order to minimize page conflicts at a double data rate (“DDR”) memory device, each client further benefits from a customized, and thus optimized, hashing algorithm. Because transaction streams arrive at the memory controller already hashed, or purposefully unhashed, the need for validating clients during a development phase is minimized.

公开(公告)号：US08717118B2

公开(公告)日：2014-05-06

申请号：US13705655

申请日：2012-12-05

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Feng Wang ,  Matthew M. Nowak

IPC: H03H7/38

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01L21/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor.

Abstract translation: 提出了倒装芯片电路组件的变压器信号耦合和阻抗匹配方法。 在一个实施例中，用于提供管芯之间的感应耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及将每个管芯组装成第一和第二 电感器被配置为变压器。 在另一个实施例中，用于使用倒装芯片技术制造的RF电路中的阻抗匹配的方法可以包括将RF输入信号传递通过使用无源过程形成的第一电感器，从而引起接近第二电感器的时变磁通量，所述第二电感器使用 激活过程，并且将由时变磁通感应的RF信号传递通过第二电感器。

公开(公告)号：US20130095576A1

公开(公告)日：2013-04-18

申请号：US13705655

申请日：2012-12-05

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Feng Wang ,  Matthew M. Nowak

IPC: H01L21/50

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01L21/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor.

Abstract translation: 提出了倒装芯片电路组件的变压器信号耦合和阻抗匹配方法。 在一个实施例中，用于在管芯之间提供电感耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及将每个管芯组装成第一和第二 电感器被配置为变压器。 在另一个实施例中，用于使用倒装芯片技术制造的RF电路中的阻抗匹配的方法可以包括将RF输入信号传递通过使用无源过程形成的第一电感器，从而引起接近第二电感器的时变磁通量，所述第二电感器使用 激活过程，并且将由时变磁通感应的RF信号传递通过第二电感器。