公开(公告)号：US09495291B2

公开(公告)日：2016-11-15

申请号：US14251626

申请日：2014-04-13

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  Anwar Q. Rohillah

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  G06F2212/1016

Abstract: A method of interleaving a memory by mapping address bits of the memory to a number N of memory channels iteratively in successive rounds, wherein in each round except the last round: selecting a unique subset of address bits, determining a maximum number (L) of unique combinations possible based on the selected subset of address bits, mapping combinations to the N memory channels a maximum number of times (F) possible where each of the N memory channels gets mapped to an equal number of combinations, and if and when a number of combinations remain (K, which is less than N) that cannot be mapped, one to each of the N memory channels, entering a next round. In the last round, mapping remaining most significant address bits, not used in the subsets in prior rounds, to each of the N memory channels.

Abstract translation: 一种通过在连续循环中迭代地将存储器的地址位映射到数量N个存储器通道来交织存储器的方法，其中在除了最后一轮之外的每个循环中：选择唯一的地址位子集，确定最大数目（L） 基于所选择的地址位子集可能的唯一组合，将N个存储器通道中的每一个映射到相等数量的组合的最大次数（F）映射到N个存储器通道，以及如果和何时一个数字 的组合保持（K小于N），N个存储器通道中的每一个输入下一轮。 在最后一轮中，将剩余的最高有效地址位映射到N个存储器通道中的每一个。

公开(公告)号：US09489305B2

公开(公告)日：2016-11-08

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： George Patsilaras ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Kris Tiri ,  Jeong-Ho Woo ,  Anwar Rohillah ,  Feng Wang ,  Moinul Khan ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US09465735B2

公开(公告)日：2016-10-11

申请号：US14045784

申请日：2013-10-03

Applicant: Qualcomm Incorporated

Inventor： Bohuslav Rychlik ,  Feng Wang ,  Anwar Rohillah ,  Simon Booth

IPC: G06F12/06

CPC classification number: G06F12/0607

Abstract: Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

Abstract translation: 公开了跨物理通道具有不均匀存储容量的存储器空间的物理信道的均匀交织的系统和方法。 交织器布置成与一个或多个处理器和系统存储器通信。 交织器识别由存储器通道支持的存储器空间中的位置，并响应于定义具有期望存储容量的虚拟扇区的逻辑。 响应于访问存储器空间的请求，交织器跨虚拟扇区均匀地访问非对称存储容量。

公开(公告)号：US20160239344A1

公开(公告)日：2016-08-18

申请号：US14623554

申请日：2015-02-17

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  George Patsilaras

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F9/5088 ,  G06F12/0811 ,  G06F12/084 ,  G06F2209/502 ,  G06F2209/505 ,  G06F2212/1024 ,  G06F2212/502

Abstract: Aspects include computing devices, systems, and methods for implementing scheduling an execution process to an execution processor cluster to take advantage of reduced latency with a victim cache. The computing device may determine a first processor cluster with a first remote shared cache memory having an available shared cache memory space. To properly schedule the execution process, the computing device may determine a second processor cluster with a lower latency to the first remote shared cache memory than an execution processor cluster scheduled with the execution process. The second processor cluster may be scheduled the execution process, thus becoming the execution processor cluster, based on a size of the available shared cache memory space and the latency of the second processor cluster to the first remote shared cache memory. The available shared cache memory space may be used as the victim cache for the execution process.

Abstract translation: 方面包括用于实现将执行过程调度到执行处理器集群以利用受害缓存的减少的延迟的计算设备，系统和方法。 计算设备可以使用具有可用共享高速缓冲存储器空间的第一远程共享高速缓冲存储器来确定第一处理器群集。 为了适当地安排执行过程，计算设备可以确定具有比执行处理调度的执行处理器群具有比第一远程共享高速缓冲存储器更低延迟的第二处理器群集。 可以基于可用的共享高速缓冲存储器空间的大小和第二处理器群集到第一远程共享高速缓冲存储器的等待时间来调度第二处理器群集，从而成为执行处理器群集。 可用的共享缓存存储器空间可以用作执行过程的受害缓存。

公开(公告)号：US10594530B2

公开(公告)日：2020-03-17

申请号：US15991759

申请日：2018-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jifeng Geng ,  Feng Wang ,  Insung Kang

IPC: H04L27/26 ,  H04B1/04 ,  G01R23/16 ,  H04W24/02

Abstract: Methods, systems, and devices for wireless communications are described. The described methods, systems, and devices may include sampling an input signal to obtain one or more signal windows. An amplitude of a first sample within a first signal window of the one or more signal windows may be determined to exceed an amplitude threshold. A series of cancellation pulses may be combined with the first sample within the first signal window to obtain a reduced signal, the reduced signal including one or more reduced samples each having an amplitudes within the amplitude threshold. The series of cancellation pulses may be based on a characteristic of the first sample. The reduced signal may then be transmitted. The series of cancellation pulses may be based on, for example, an envelope of the first sample. In some cases, the series of cancellation pulses may be based on a phase of the first sample.

公开(公告)号：US09690710B2

公开(公告)日：2017-06-27

申请号：US14598049

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Feng Wang ,  Bohuslav Rychlik ,  Moinul Khan

IPC: G06F12/00 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0868

CPC classification number: G06F12/0888 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0835 ,  G06F12/0868 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/62 ,  Y02D10/13

Abstract: Systems and methods for improved operation of a victim cache in a portable computing device (PCD) are presented. A lower level cache is operated as a victim to an upper level cache, the lower level cache containing a plurality of cache lines. A filter is operated in association with the lower level victim cache, and reflects the cache lines contained in the victim cache. For a miss at the upper level cache, the filter is checked to determine if the requested cache line is in the victim cache. If checking the filter determines that the requested cache line is in the victim cache the requested cache line is retrieved from the victim cache. If checking the filter determines that the request cache line is not in the victim cache, the victim cache is bypassed and the cache line is requested from a memory controller.

公开(公告)号：US09582329B2

公开(公告)日：2017-02-28

申请号：US14623554

申请日：2015-02-17

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  George Patsilaras

IPC: G06F9/54 ,  G06F9/50 ,  G06F12/08

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F9/5088 ,  G06F12/0811 ,  G06F12/084 ,  G06F2209/502 ,  G06F2209/505 ,  G06F2212/1024 ,  G06F2212/502

Abstract: Aspects include computing devices, systems, and methods for implementing scheduling an execution process to an execution processor cluster to take advantage of reduced latency with a victim cache. The computing device may determine a first processor cluster with a first remote shared cache memory having an available shared cache memory space. To properly schedule the execution process, the computing device may determine a second processor cluster with a lower latency to the first remote shared cache memory than an execution processor cluster scheduled with the execution process. The second processor cluster may be scheduled the execution process, thus becoming the execution processor cluster, based on a size of the available shared cache memory space and the latency of the second processor cluster to the first remote shared cache memory. The available shared cache memory space may be used as the victim cache for the execution process.

Abstract translation: 方面包括用于实现将执行过程调度到执行处理器集群以利用受害缓存的减少的延迟的计算设备，系统和方法。 计算设备可以使用具有可用共享高速缓冲存储器空间的第一远程共享高速缓冲存储器来确定第一处理器群集。 为了适当地安排执行过程，计算设备可以确定具有比执行处理调度的执行处理器群具有比第一远程共享高速缓冲存储器更低延迟的第二处理器群集。 可以基于可用的共享高速缓冲存储器空间的大小和第二处理器群集到第一远程共享高速缓冲存储器的等待时间来调度第二处理器群集，从而成为执行处理器群集。 可用的共享缓存存储器空间可以用作执行过程的受害缓存。

公开(公告)号：US09558117B2

公开(公告)日：2017-01-31

申请号：US14597992

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Feng Wang ,  Bohuslav Rychlik ,  Moinul Khan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0848 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/282 ,  G06F2212/283 ,  G06F2212/6012 ,  G06F2212/604

Abstract: Systems and methods for adaptive implementation of victim cache modes in a portable computing device (PCD) are presented. In operation, an upper level cache is partitioned into a main portion and a sample portion; and a lower level cache is partitioned into a corresponding main portion and sample portion in communication with the main portion and sample portion of the upper level cache. A victim mode sample data set and a normal mode sample data set are obtained from the lower level cache. Based on the victim mode and a normal mode sample data sets, a determination is made whether to operate the lower level cache as a victim to the upper level cache. The main portion of lower level cache is caused to operate either as a victim or non-victim to the main portion of the upper level cache in accordance with the determination.

Abstract translation: 提出了在便携式计算设备（PCD）中自适应实现受害者缓存模式的系统和方法。 在操作中，上级缓存被分割成主要部分和样本部分; 并且下级缓存被分割成与上级高速缓存的主要部分和采样部分通信的对应主要部分和采样部分。 从下级缓存获得受害者模式样本数据集和正常模式样本数据集。 基于受害者模式和正常模式的采样数据集，确定是否将较低级别的高速缓存操作为上级缓存的受害者。 下级缓存的主要部分根据该确定被作为高级缓存的主要部分作为受害者或不受害者操作。

公开(公告)号：US20140206105A1

公开(公告)日：2014-07-24

申请号：US14221324

申请日：2014-03-21

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Feng Wang ,  Matthew Michael Nowak

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01L21/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor.

Abstract translation: 提出了倒装芯片电路组件的变压器信号耦合和阻抗匹配方法。 在一个实施例中，用于在管芯之间提供电感耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及将每个管芯组装成第一和第二 电感器被配置为变压器。 在另一个实施例中，用于使用倒装芯片技术制造的RF电路中的阻抗匹配的方法可以包括将RF输入信号传递通过使用无源过程形成的第一电感器，从而引起接近第二电感器的时变磁通量，所述第二电感器使用 激活过程，并且将由时变磁通感应的RF信号传递通过第二电感器。

公开(公告)号：US20190372817A1

公开(公告)日：2019-12-05

申请号：US15991759

申请日：2018-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jifeng Geng ,  Feng Wang ,  Insung Kang

IPC: H04L27/26 ,  H04B1/04

Abstract: Methods, systems, and devices for wireless communications are described. The described methods, systems, and devices may include sampling an input signal to obtain one or more signal windows. An amplitude of a first sample within a first signal window of the one or more signal windows may be determined to exceed an amplitude threshold. A series of cancellation pulses may be combined with the first sample within the first signal window to obtain a reduced signal, the reduced signal including one or more reduced samples each having an amplitudes within the amplitude threshold. The series of cancellation pulses may be based on a characteristic of the first sample. The reduced signal may then be transmitted. The series of cancellation pulses may be based on, for example, an envelope of the first sample. In some cases, the series of cancellation pulses may be based on a phase of the first sample.